MFIS ferroelectric memory array on SOI and method of making...

Details MFIS ferroelectric memory array on SOI and method of making... MFIS ferroelectric memory array on SOI and method of making...

2006-01-31

2006-01-31

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S151000

Reexamination Certificate

active

06991942

ABSTRACT:
An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.

REFERENCES:
patent: 6531324 (2003-03-01), Hsu et al.
patent: 6711049 (2004-03-01), Hsu et al.
patent: 2004/0142579 (2004-07-01), Morita et al.

Affiliated with

Also associated with

Rating

MFIS ferroelectric memory array on SOI and method of making... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with MFIS ferroelectric memory array on SOI and method of making..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MFIS ferroelectric memory array on SOI and method of making... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3578028