Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure
Reexamination Certificate
1998-12-14
2001-11-13
Pham, Long (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
C257S578000, C257S583000, C257S591000
Reexamination Certificate
active
06316817
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to bipolar junction transistors and in particular to bipolar junction transistors formed in the same integrated circuit with complimentary metal-oxide-semiconductor transistors (BiCMOS). Still more particularly, the present invention relates to formation of bipolar transistors with reduced vertical collector resistance.
2. Description of the Related Art
Silicon technologies that employ both complimentary metal-oxide-semiconductor (CMOS) and bipolar devices on the same silicon substrate (BiCMOS) provide an excellent solution to many types of mixed-signal chip designs.
FIGS. 1A
,
1
B depicts a known simple, low cost NPN bipolar device commonly employed in BiCMOS designs along with the mask levels used to form this device. The bipolar device
100
is formed in a heavily-doped substrate
102
, on which a lightly doped epitaxial layer
104
has been deposited. A field oxide
106
is grown for device isolation. A silicon nitride layer (not shown) prevents growth of the field oxide
106
in the region of the device window
108
.
Buried collector
110
is typically implanted, followed by formation of the collector region
112
. A masking layer (not shown) is provided to allow base region
114
to be formed through a base region window
116
in the masking layer. Emitter region
118
and collector contact region
120
are similarly formed by windows
122
,
124
through a masking layer (not shown). Emitter (E), base (B), and collector (C) contacts
126
,
128
and
130
, respectively, are formed through contact openings
132
. The process results in vertically integrated NPN bipolar device
100
.
Critical to the slew-rate performance of vertically integrated bipolar junction transistors is the collector resistance.
FIG. 2A
illustrates the collector resistance of vertically integrated bipolar junction transistors through the bipolar device of
FIGS. 1A
,
1
B and
FIG. 2B
illustrates equivalent circuit diagram. As shown in
FIG. 2B
the bipolar device of
FIGS. 1A and 1B
may be represented as a bipolar transistor
202
with a resistor
204
at the collector having a resistance of R
c
. Collector resistance R
c
has both a vertical component, arising from the vertical distance (L
4
-L
2
) between collector contact
130
and the body of the collector, and a lateral component, arising from the horizontal distance (L
3
-L
1
) between the emitter and collector contacts
126
and
130
.
Both components are significant to bipolar device performance.
FIG. 3A
depicts the prior art method of minimizing collector resistance to optimize device performance. Buried layer formation, producing a heavily doped layer (buried collector or subcollector
110
) deep within the collector, reduces the lateral component of collector resistance R
c
.
A “sinker” formation
302
in the collector contact region is typically used to minimize the vertical component of collector resistance R
c
. However formation of sinker
302
typically requires additional process steps.
It would be advantageous to be able to reduce both the vertical and lateral components of the collector resistance in a device without adding significantly to the process steps required to form a vertically integrated bipolar device. It would be desirable to be able to reduce both the vertical and lateral components of the collector resistance simultaneously.
SUMMARY OF THE INVENTION
High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a vertically integrated bipolar device. The need for a sinker implant or other additional steps to reduce collector resistance is avoided. The necessary processing modifications may be readily integrated into conventional bipolar or BiCMOS process flows.
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Tamba A et al: Characteristics of Bipolar Transistors with Various Depth N+ Buried Layers Formed by High Energy Ion Implantation; Extended Abstracts for the International Conference on Solid State Devices and Materials; Tokyo, Aug. 24-26, 1988; no Conf. 20, Aug. 24, 1988, Japan Society of Applied Physics; pp. 141-144; XP000042517.
Characteristics of Bipolar Transistors with Various Depths of n+Buried layers Formed by High-Energy Ion Implantation, Akihiro Tamba, Yutaka Kobayashi, Tadashi Suzuki and Nobuyoshi Natsuaki, Japanese Journal of Applied Physics, pp. 156-160.
Daniel David W.
Randazzo Todd A.
Seliskar John J.
Coleman William David
LSI Logic Corporation
Pham Long
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