Metrology for monitoring a rapid thermal annealing process

Details Metrology for monitoring a rapid thermal annealing process Metrology for monitoring a rapid thermal annealing process

2002-06-20

2004-08-17

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

C438S015000, C324S765010

Reexamination Certificate

active

06777251

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor meteorology, and more particularly to a new meteorology for monitoring a rapid thermal annealing process.
BACKGROUND OF THE INVENTION
One of the most important properties of semiconductor materials is that the semiconductor material conductivity can be controlled by adding dopants. Semiconductor materials such as silicon (Si), germanium (Ge), and gallium-arsenate (GaAs) are doped with either n-type or p-type dopants in typical integrated circuit fabrication processes. Heretofore, diffusion and ion implantation have been the two primary methods used to doped semiconductors. However, in modern integrated circuit fabrication processes, doping is mainly accomplished by ion implantation.
Pure single-crystal silicon has a high resistivity, and the more pure the crystal, the higher the resistivity. The conductivity of single-crystal silicon can be improved by adding dopants, such as boron (B), phosphorus (P), arsenic (As) or antimony (Sb). Boron is a p-type dopants with only three electrons in the outer valence shell or orbit. A boron atom provides a hole by replacing a silicon atom (that has four electrons in the outer valence shell) in the single-crystal silicon lattice. Holes can carry electrical current which acts as a positive charge. Semiconductor devices doped with boron are called p-type semiconductors. Phosphorus, arsenic and antimony atoms have five electrons in the outer valence shell so they can provide electrons to conductive electrical current when they replace a silicon atom in the single-crystal silicon wafer. Because the electron has a negative charge, phosphorus, arsenic and antimony are called n-type dopants, and the semiconductors with these dopants are called n-type semiconductors.
Traditionally, doping was accomplished using a diffusion process in high-temperature furnaces. The area where the furnaces were located was called the diffusion bay, and the furnaces were called diffusion furnaces, even though the furnaces have been used for diffusion or other processes such as oxidation or annealing. Currently, few diffusion doping processes are performed in advance integrated circuit manufacturing facilities, and the furnaces have been used mainly for oxidation and annealing. However, the furnace area in most integrated circuit fabrication facilities is still called the diffusion bay and the furnaces are still called diffusion furnaces.
The diffusion process usually involves multiple steps. A dopant oxide layer is normally deposited on the wafer surface in a predeposition process. Thereafter, an oxidation process converts the dopant oxide into silicon dioxide and forms a high concentration of dopant in the silicon substrate near the silicon-silicon dioxide interface. A high-temperature drive-in process diffuses the dopant atoms into the substrate to the depth required for desired devices. The three processes: predeposition; oxidation; and drive-in; are high temperature processes usually taking place in furnaces. After the dopant drive in, the oxide layer is stripped by a wet etching process.
However, the diffusion process has a number of limitations. The dopant concentration and junction depth cannot be independently controlled, because both are strongly related to the diffusion temperature. Another major disadvantage is that the dopant profile is always isotropic due to the nature of the diffusion process. Consequently, an alternative and better process was being sought of those working in the art.
An ion implantation process provides for much better control of doping than the diffusion process. Ion implantation adds dopant atoms into the silicon wafer using energetic ion beam injection. Contrary to the diffusion process, ion implementation can independently control both dopant concentration and junction depth. The dopant concentration can be controlled by the combination of ion beem current and implantation time, and the junction depth can be controlled ion energy. The ion implantation process can dope the silicon with a wide range of doping concentrations ranging from 10
11
to 10
17
atoms/cm
2
. Although the diffusion process requires a thick oxide to be grown as the diffusion mask, ion implantation is a room temperature process, and a thick layer of photoresist can block the energetic dopant ions. Ion implantation can use photoresist as the patterning mask and does not need to grow silicon dioxide to form a hard mask as was required by the diffusion process. However, the wafer holder of an ion implanter must have a cooling system to take away the heat generated by the energetic ions and to prevent photoresist reticulation.
A mass analyzer of an ion implanter selects exactly the correct ion species needed for ion implantation and generates a pure ion beam thus eliminating the possibility of contamination. The ion implantation process is operated in a high vacuum, clean environment, and is anisotropic. Dopant ions are implanted into silicon primarily in a vertical direction, and the doped region clearly reflects the area identified by the photoresist mask. This is in contrast to the diffusion process which is isotropic and wherein the dopant always diffuses laterally underneath the silicon dioxide mask.
When ions bombard and penetrate the silicon substrate, they collide with lattice atoms. The ions generally lose their energy and eventually stop inside the silicon. There are two stopping mechanisms that are known. One is when the implanted ions collide with nuclei from the lattice atoms, are scattered significantly by collision, and transfer energy to the lattice atoms. This is called the nuclear stopping. In this hard collision, lattice atoms may receive enough impact energy to break free from the lattice binding energy which causes crystal structure disorder and damage. Another stop mechanism is when incidental ions collide with electrons of the lattice atoms. The incidental ion path in the electronic collision is almost unchanged, energy transferred is very small, and crystal structure damage is minimal. This soft collision is called electronic stopping.
The ion energy of the ion implantation process range from also low energy of 0.5 keV for ultra-shallow junctions to high-energy of 1 MeV for well implantation. In general, the higher the ion energy the deeper the ion can penetrate into the substrate. However, even with the same implantation energy, ions don not stop exactly at the same depth in the substrate because the ions each have different collisions with different atoms. The projected ion penetration range always has a distribution.
Higher energy ion beams can penetrate deeper into the substrate, and therefore have a longer projected ion penetration range. Since smaller ions have smaller collision cross-sections, smaller ions at the same energy level can penetrate deeper into the substrate and the mask materials.
The projected penetration range of an ion in an amorphous material always follows a Gaussian distribution, also called the normal distribution. In a single-crystal silicon, the lattice atoms have an orderly arrangement, and many channels can be seen at different angles. If an ion enters the silicon at the right angle, it can travel long distance with very little energy if it enters the channel. This is called channeling effect. The channeling effect causes some ions to penetrate deeply into the single-crystal substrate. This can form a “tail” on the normal dopant distribution curve. It is an undesirable dopant profile which could affect the electronic device performance. Therefore, several methods have been used to minimize this effect.
One way to minimize the channeling effect is ion implantation on a tilted wafer, which typically is tilted an angle ranging from 0-7 degrees. When a tilted wafer is used, ions impact the wafer at an angle and cannot reach the channel. The incident ions have nuclear collisions right away, and effectively reduce the channeling effect. Most ion implantation processes use this technique to minimize channeling effect and most wafer holders used with an io

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