Metrics for specifying and/or testing neural networks

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395 24, 36455101, G06E 100, G06E 300, G06F 1518

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active

055509517

ABSTRACT:
A method for testing a neural network, and apparatus for carrying out the method. A first embodiment of the method includes the steps of (a) providing a neural network having a set of connection values, (b) stimulating at least one input of the neural network with an input vector to obtain output signals at an output of the neural network, (c) obtaining a plurality of samples of the output signals, wherein at least one of the plurality of samples is delayed in time from another one of the samples, and wherein at least one of the plurality of samples may represent a difference between two samples, (d) generating an image from the plurality of samples, and (e) comparing the image to a reference image to determine an operational characteristic of the neural network. The step of generating generates an image that is comprised of a plurality of points, wherein each of the points is referenced to an x-y coordinate system, wherein a distance along the x-axis is a function of a value of the output of the neural network for a given input vector applied to a first input of the neural network, and wherein a distance along the y-axis is function of a value of the output of the neural network for the given input vector applied a second input of the neural network.

REFERENCES:
patent: 4094307 (1978-06-01), Young, Jr.
patent: 4912647 (1990-03-01), Wood
patent: 5164912 (1992-11-01), Osborne et al.
On Testing Iterated neural network Structures A. Moore et al. 10-12 Mar. 1 IEEE, Int Conf on Computer design.
Testing of Analog Neural Array-Processor Chips W-J. Hsu et al IEEE 14-16 Oct. 1991, Int. Conf. on Computer design.

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