Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2006-01-17
2006-01-17
Wilson, Christian (Department: 2891)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S738000
Reexamination Certificate
active
06987068
ABSTRACT:
Embodiments of methods in accordance with the present invention provide a planarized surface between a semiconductor device and a portion of surrounding passivation material. The methods involve the use of a hard mask that defines the planarized surface as the interface between the hard mask and both the passivation layer and the device, after a passivation layer etching process. The resulting planarized surface has a small to zero step height, is insensitive to passivation layer non-uniformity and etch non-uniformity, provides full passivation of the device side wall, provides protection for the device against etch-induced damage, and prevents the detrimental effects of passivation layer voids. The methods are applicable to semiconductor device fabrication for electronic and photonic systems such as, but not limited to, cell phones, networking systems, high brightness (HB) light emitting diodes (LEDs), laser diodes (LDs), and multijunction solar cells.
REFERENCES:
patent: 4356056 (1982-10-01), Cornette et al.
patent: 5286665 (1994-02-01), Muragishi et al.
patent: 5472564 (1995-12-01), Nakamura et al.
patent: 5895273 (1999-04-01), Burns et al.
patent: 6004853 (1999-12-01), Yang et al.
patent: 6077789 (2000-06-01), Huang
patent: 6235638 (2001-05-01), Huang et al.
patent: 6399469 (2002-06-01), Yu
patent: 6528363 (2003-03-01), Ku et al.
patent: 6541320 (2003-04-01), Brown et al.
patent: 6583469 (2003-06-01), Fried et al.
patent: 6593243 (2003-07-01), Kimura
patent: 6767835 (2004-07-01), Nariman et al.
patent: 6812119 (2004-11-01), Ahmed et al.
patent: 2352874 (2001-07-01), None
patent: 60235436 (1985-11-01), None
patent: 06021432 (2004-01-01), None
Friis Peter
Hanberg Jesper
Intel Corporation
Schwabe Williamson & Wyatt P.C.
Wilson Christian
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