Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2000-01-20
2001-07-24
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S393000
Reexamination Certificate
active
06265230
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to semiconductor integrated circuits including ferroelectric memory cells. The invention relates particularly to ferroelectric memory elements integrated on a silicon substrate.
BACKGROUND ART
Ferroelectric memory circuits have been proposed as a substitute for silicon memory circuits, such as dynamic random access memory (DRAM), static random access memory (SRAM), and electrically alterable read-only memory (EAROM). DRAM is the most inexpensive of these memories, but it needs to be refreshed every few milliseconds and is considered to be relatively slow. SRAM needs no refreshing as long as the power stays applied, and it is relatively fast, but it requires a large amount of power relative to DRAM. Furthermore, its memory states disappear if power is removed. EAROM has generally high access rates, and it is non-volatile upon the removal of power, but its writing time is slow and the number of writing cycles is generally limited. Furthermore, it does not form in dense integrated circuits.
Ferroelectric memory (FRAM) offers the promise of overcoming the limitations stated above. FRAM is based on the same fundamental storage concept as DRAM, a storage capacitor in which is stored or not stored a charge representing a memory state. However, in a FRAM the capacitor core includes a ferroelectric material that can be electrically poled into either of two stable polarization states. Once poled into one of these states, the ferroelectric capacitor remains in that state even if power is removed, and its charge state can be read after the FRAM is subsequently powered up. As a result, it provides the non-volatile storage representative of EAROM. However, it can generally be read and written at speeds representative of DRAM and SRAM. It offers much lower power consumption than DRAM or SRAM because no powering or refreshing is required for storage. Furthermore, the high charge storage available in the ferroelectric material of dielectric constant and the resemblance to DRAM means that FRAM memories can be integrated to very high densities. Yet further, the high charge storage increases the cell's resistance to various types of radiation effects.
However, if FRAM it to be commercially viable, it must be integrated on silicon substrates, either so that the silicon provides support functions such as read, write, and gating circuitry for large-scale FRAM or so that the F.RAM serves as auxiliary memory for silicon logic. The integration of ferroelectrics with silicon has proven difficult. Two principal problems have been the diffusion of oxygen from the ferroelectric cell into the underlying silicon substrate and the deleterious effects upon the ferroelectric of the hydrogen anneal usually required for silicon integrated circuits.
Ferroelectrics are almost invariably based upon highly oxidized metal crystals or polycrystals such as PbTi
1−x
Zr
x
O
3
(PZT). PZT has a simple lattice structure represented in the crystalline unit cell representation in
FIG. 1
, which is a tetragonal unit cell having equal a and b axes and a slightly larger c axis so that the cell is approximately cubic. The lead (Pb) atoms
10
having a charge state of +2 occupy the corners of the tetragonal cell, the oxygen (O) atoms
12
having a charge state of −2 occupy the faces of the cell, and the titanium (Ti) or zirconium (Zr) atom having a charge state of +4 occupies approximately the cell center. Above the Curie temperature (T
c
), the cell is cubic (a=b=c), but below the Curie temperature the cell assumes the somewhat non-cubic structure of FIG.
1
. The Ti or Zr atom does not occupy the exact center of the cell but instead can occupy one of two equivalent positions
14
a
,
14
b
slightly above or below the center along the c-axis. Both of these states are stable under operational conditions and represent the two polarization states of the Ti and Zr cations relative to the O anions. Other ferroelectrics have different and possibly more complex structures, but most have a structure sharing chemical effects with those of PZT.
A thin layer of a ferroelectric material such as PZT is typically deposited or at least annealed in a high-temperature, oxygen-rich ambient. Usually, the temperature is above the Curie temperature, which for PZT is about 390° C. For silicon integration, the ferroelectric layer is deposited and processed after the silicon level has been processed. Such high-temperature processing in an oxygen environment is considered to be disadvantageous if not fatal for a silicon circuit.
In the older, conventional techniques for fabricating ferroelectric cells, the ferroelectric layer is deposited by sol-gel or other processes which produce a randomly oriented polycrystalline ferroelectric layer. This crystalline structure has the disadvantage of large inter-granular boundaries along which oxygen can propagate from the oxygen-rich ferroelectric to the underlying silicon, at the boundary of which the oxygen and silicon react to form silicon dioxide, producing a strongly electrically insulative layer. Platinum (Pt) has long been proposed as an interfacial barrier between the ferroelectric and the underlying silicon. Although platinum is a relatively noble material, it has been found to be a poor barrier for oxygen migration from the ferroelectric to the underlying silicon.
Ramesh and his group have disclosed in various patents and publications (see, for example, U.S. Pat. No. 5,798,903) the technique of avoiding the problems associated with polycrystalline ferroelectrics by epitaxially growing a crystallographically oriented ferroelectric layer on a metal-oxide layer, which also acts as an electrode. The metal-oxide layer either itself provides a crystallographically templating function or is epitaxially grown on another crystallographically templating layer. A templating layer self-aligns to a thermodynamically preferred crystalline orientation, even when grown on an unaligned substrate, and thereafter serves as a crystallographic template for epitaxial growth of over layers. The early templating layers were the layered (distinctly non-cubic) perovskites, but cubic perovskites, such as lanthanum strontium cobalate (LSCO) have been shown to effectively template after grown perovskite layers. The crystallographically oriented ferroelectric layer reduces the area of inter-granular boundaries, thus reducing the amount of oxygen diffusion from the growing ferroelectric to the underlying silicon. Furthermore, Dhote and Ramesh in U.S. Pat. No. 5,777,356, incorporated herein by reference in its entirety, have disclosed the use of an effective barrier to oxygen diffusion placed between the lower metal oxide electrode and the silicon, specifically an intermetallic metal such as Ti
3
Al, although many other compositions are possible.
A ferroelectric random access memory (FRAM) cell
20
is illustrated in the cross-sectional view of FIG.
2
. Many such memory cells are formed in an integrated circuit memory together with silicon-based support circuitry on a <001>-oriented crystalline silicon substrate
22
. Each cell includes both a ferroelectric capacitor and a silicon transistor gating the ferroelectric capacitor to read and write lines. The metal-oxide-semiconductor (MOS) transistor is created in part by forming source and drain wells
24
,
26
having a conductivity type opposite to that of the substrate
22
. The intervening gate region is overlaid with a gate structure
28
including an unillustrated thin gate oxide facing the silicon gate region G and an unillustrated upper metal gate line, for example of aluminum, to control the gate.
A first inter-level dielectric layer
30
is deposited over the substrate and the transistor structure. A through hole
32
is etched through the first inter-level dielectric layer
30
in the area over the source well
24
, and polysilicon is filled into the through hole
32
to form a polysilicon contact plug to the transistor source. A metal source line
34
is photolithographically
Aggarwal Sanjeev
Perusse Scott Robert
Ramesh Ramamoorthy
Brewster William M.
Fahmy Wael
Hey David A.
Telcordia Technologies Inc.
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