Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2001-02-22
2004-01-20
Han, Jessica (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S283000
Reexamination Certificate
active
06680604
ABSTRACT:
BACKGROUND OF THE INVENTION
Use of Dual Mode Processors and Droop in Mobile Computer Applications
Modern notebook computers employ advanced processors with high clock rates that place higher demand on the battery life and impose higher thermal stresses on to the circuit components. To enable systems with higher performance without compromising battery life, dual mode processors were introduced. These processors operate on higher clock rates and higher voltage when the notebook is powered from the wall adapter (so-called “performance mode”). When battery power is used, the operating voltage and the clock frequency are simultaneously scaled down to reduce the consumed power without greatly compromising the computing performance. This is so-called “battery-optimized mode”. In battery-optimized mode consumed power is about 40% less than during performance mode with almost equal contribution from the frequency and the voltage scaling.
Power dissipated by a processor is proportional to the clock frequency and to the applied voltage squared.
P
CPU
=K×F
CPU
×V
CPU
2
(1)
Considering that the processor power is a product of the operation voltage and the current P
CPU
=V
CPU
×I
CPU
, the processor current is proportional to the processor operating frequency and the voltage applied.
I
CPU
=K×F
CPU
×V
CPU
(2)
Many computer power management systems deliberately “droop” the CPU voltage to control impedance of the DC/DC converters and to reduce the number of the capacitors required to handle the processor supply current transients. The output voltage of the converter with a droop is inversely proportional to the load current. Reduced power is a key benefit of using the DC/DC converter with a droop to power the processor in the notebooks or other mobile applications with power and thermal constrains. Because the processor power is proportional to the supply voltage squared, even small reductions in the output voltage within the tolerance window translate into measurable reductions in the power dissipated. The additional power reduction may be about 10% and results in extra battery life.
Known Method of Droop Implementation
The
FIG. 1
illustrates one known method of implementing droop in the DC/DC converter. The converter
10
includes a DC source VIN that is selectively coupled to a power switch
14
. The switch
14
may include one or more power devices in the form of a bridge. The output current I
O
is connected to the load RL via an inductor
24
and a capacitor
26
. The output current is sensed as current I
CS
and is connected to a current gain circuit
30
. The output of the current gain circuit is the current I
DROOP
. It is coupled to a node
36
at one input of error amplifier
50
. Also connected to the node
36
is resistor R
1
and the RC feedback circuit of C
COMP
and R
COMP
. The other input to the error amplifier is provided by the digital to analog converter (DAC)
40
and buffer amplifier
42
. They set the reference voltage for the error amplifier
50
. The output of the error amplifier is connected to one input of a comparator
60
. Its other input receives a ramp signal. The output of the comparator is connected to a latch
18
that is controlled by a clock signal CLK. The output of the latch
18
controls the operation of the power switch
14
to the turn the DC power on and off.
The sensed current signal I
CS
is proportional to the load current I
o
, I
CS
can be either inductor current, or switch current, or diode (or synchronous switch) current. It is scaled down and transformed into the current I
DROOP
that creates a feedback signal as the voltage drop across the resistor R
1
. At the input of the voltage-loop error amplifier I
DROOP
is summed with the voltage feedback signal. As a result, the output voltage of the converter
10
is lowered proportionally to the sum of the droop and load currents. In other words, by changing the fed back voltage from the load voltage to the load voltage less the desired droop, the output of the error amplifier and the power supply is adjusted to provide the desired droop.
The output voltage of the loaded converter varies in accordance with the following equation.
V
CPU
(
I
)=
V
CPU
(0)−
V
DROOP
(
I
), (3)
Where:
V
CPU
(0)=V
DAC
×(1+&Dgr;/2)—is the output voltage with no load. This voltage is usually somewhat higher then nominal voltage commanded by the DAC reference. Normally, the droop is centered to the half-load current. It means that at half-load current the output voltage is equal to the voltage commanded by the DAC.
&Dgr;—is the desired droop value given as a fraction of the V
DAC
.
V
DROOP
(I)=R
1
×G
C
×I
CPU
—is the droop in the output voltage due to load current—proportional voltage-drop across the resistor R
1
. The above droop circuit and other droop circuits are shown and described in U.S. patent application Ser. No. 09/591,560 filed Jun. 9, 2000, assigned to the owner of this invention and incorporated herein by reference.
Problems with Conventional Droop Implementation
When the dual mode processors are used, it is desired to have an adequate droop (equal fractions of the commanded output voltage) in both modes of operation. The known droop method does not provide relatively equal droop for the different operation modes because the gain in the current feedback loop is constant. Indeed, constant gain is a fundamental characteristic of conventional negative feedback circuit designs.
Using (2) and (3), the equation for the converter 10 output voltage can be obtained in the following form, which shows that the converter output voltage is not only inversely proportional to the load current but is also inversely proportional to the processor clock frequency F
CPU max
.
V
CPU
(
I
)
=
V
DAC
(
1
+
Δ
2
)
-
R1
×
G
C
×
K
×
F
CPU
max
×
K
f
×
V
CPU
(
I
)
V
CPU
(
I
)
=
V
DAC
×
(
1
+
Δ
2
)
1
+
R1
×
G
C
×
K
×
F
CPU
max
×
K
f
(
4
)
Where:
F
CPU max
×K
ƒ
represents variable processor performance, which varies due to modulating multiplier K
ƒ
=0 . . . 1. This multiplier simulates the factor how the processor is engaged by the software. When K
f
=0, the processor idles and its current is close to zero. When K
f
=1, the performance and the load current have their maximum values. This model is involved for illustrative purposes only to evaluate the considered solutions and does not cover all the aspects of the processor operation.
The value of the gain constant G
C
for circuit
30
of converter
10
can be found as:
G
C
=
2
×
Δ
(
2
-
Δ
)
×
R1
×
K
×
F
CPU
max
.
(
5
)
The droop is usually tuned to handle the worst case transient that is associated with the performance mode where the processor current is high. When the processor is switched to operate in the battery mode, the operating frequency and voltage are scaled down. In this case, the processor current is significantly lower, the droop is much smaller and its benefits deteriorated. If gain was tuned to create the optimal droop for the battery-optimized mode, the droop becomes excessive in the performance mode.
The following examples illustrate this asymmetrical feature of droop versus processor mode. For example, a known dual mode processor has the following power parameters at high performance mode: V1=1.6 V, Imax=10.2 A, F=600 MHz, where V is the processor voltage, Imax—is the maximum processor current, F—is the clock frequency. In the battery mode these parameters are V2=1.35 V, Imax 6.8 A, F=500 MHz. The current feedback gain is set to achieve 5% droop. In the first case, the droop is tuned to the performance mode. In the second case, the droop is tuned to be optimal in the battery-optimized mode. In both cases the processor constant is equal to 10.5 n
Coletta Michael
Muratov Volodymyr A.
Wiktor Wlodzimerz S.
Fogg and Associates LLC
Han Jessica
Intersil Corporation
Lundberg Scott V.
LandOfFree
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