Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-10-19
2004-02-17
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S693000, C252S079100
Reexamination Certificate
active
06693035
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention described pertains to the polishing methods and slurry formulations used in the planarization of integrated circuit surfaces containing various films, most particularly those of a metal, a barrier or liner layer, and a dielectric layer.
2. Related Art
One of the critical requirements necessary in the production of increasingly complex and dense semiconductor structures is the ability to retain planarity. Without the ability to planarize, the complexity and density of the structures constructed on a semiconductor wafer are greatly limited. Chemical-Mechanical Planarization, or CMP, is an enabling technology in this area, since it has proved to be the most effective method used to planarize surface films on semiconductor substrates.
While the first applications of CMP technology focused on the polishing of dielectric films (i.e., SiO
2
), polishing of metal structures used for circuit interconnects is increasing rapidly. Along with the increase in metal planarization is a inherent increase in the number of different films that are simultaneously polished. Most metal structures contain three different films: a conductive metal layer, a barrier (or liner) layer between the conductive metal layer and the adjacent dielectric layer, and a dielectric layer. It is often desirable for the removal rates of each film to differ from each other in order to induce planarity and maintain the integrity of the semiconductor structure during polishing. In a typical metal structure, for example, if the entire planarization step were to take place in one step of polishing, it would typically be desirable to have high removal rates of material for the metal and barrier layers, while having low removal rates for the dielectric layer.
However, while it is certainly desirable to limit the number of processing steps, there are often inherent difficulties associated with a one-step process that limit it's usefullness. For example, copper interconnects, coupled with low-k dielectrics, have the potential (when compared to Al/SiO
2
) to increase chip speed, reduce the number of metal layers required, minimize power dissipation, and reduce manufacturing costs. A typical copper interconnect structure contains a conductive copper film, a barrier layer of tantalum or tantalum nitride, and a dielectric layer of silicon dioxide. In one-step copper CMP, it is desirable to remove the Cu and Ta/TaN barrier layer as fast as possible, while removing the SiO
2
dielectric layer as slow as possible. However, this is often difficult, since the regimes in which Cu and Ta exhibit comparable removal rates often do not overlap. Also, it is critical to maintain the underlying semiconductor structure regardless of the removal rates of the various films. For the Cu CMP example, the removal of Cu within the interconnect features (called “dishing” or “recess”) is undesirable since optimal electrical performance is obtained when as much of the conducting metal line as possible remains. Also, it is also desirable to minimize the removal of the SiO
2
dielectric layer within interconnect structures (called “erosion”).
To give satisfactory results in Cu CMP, Landers et al. in U.S. Pat. No. 5,676,587 have proposed a two-step polishing process to be used with Cu interconnect structures. The first step is designed to remove most of the overburden of Cu, and the second step is designed to remove the barrier or liner layer of Ta, TaN, Ti, or TiN. For the second step, a silica based slurry of near-neutral pH is detailed. However, U.S. Pat. No. 5,676,587 does not detail the specific removal rate requirements of the second step slurry. Farkas et al. in U.S. Pat. No. 5,773,364 presents the use of ammonium salts as oxidizers in metal CMP slurries. Farkas et al. in U.S. Pat. No. 5,614,444 discusses the use of materials with a polar and apolar component in silica-based slurries for the suppression of SiO
2
removal rate during metal CMP processes. The use of quaternary ammonium salts as an example of a cationic compound is listed.
SUMMARY OF THE INVENTION
A method is provided for polishing a composite semiconductor structure containing a conducting metal interconnect layer, an insulating dielectric layer, and a barrier layer between the two: most preferably, a copper metal layer, a silicon dioxide dielectric layer, and a barrier layer of tantalum. The method involves a two-step polishing process: in the first step, the majority of the conducting metal layer is removed without removing significant amounts of either the barrier layer or the dielectric layer. In the second step, the metal interconnect remaining on the horizontal portions of the barrier layer and the barrier layer are removed without removing significant amounts of the dielectric layer, and without degrading the integrity of the remaining structure by significant removal of the remaining metal layer (commonly called “dishing” or “recess”) or removal of significant amounts of the remaining dielectric layer (commonly called “erosion”).
Preferred methods of the invention are:
a method for chemical-mechanical polishing of a semiconductor structure comprised of a conductive metal interconnect layer, a barrier or liner film, and an underlying dielectric layer, wherein the method consists of the following steps:
a) removal of the majority of the metal layer using a first-step slurry that has high selectivity between the metal layer and the barrier layer;
b) removal of the barrier layer using a second-step slurry that has a high barrier removal rate, a low metal layer removal rate, a low dielectric layer removal rate and wherein the second-step slurry has a pH which is basic and, a method for chemical-mechanical polishing of a semiconductor structure comprised of a conductive metal interconnect layer, a barrier or liner film, and an underlying dielectric layer, wherein the method consists of the following steps:
a) removal of the majority of said metal layer using a first-step slurry that has high selectivity between said metal layer and said barrier layer;
b) removal of said barrier layer using a second-step slurry that has a high barrier removal rate, a metal layer removal rate between high and low, a low dielectric layer removal rate and wherein said second-step slurry has a pH which is basic.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
An improved method of the CMP polishing of metal interconnect structures. This method is applicable to any metal interconnect structure containing: a conductive metal (such as Cu, Al, or W), a barrier or liner layer (such as Ta, TaN, Ti, or TiN), and an underlying ILD structure (such as SiO
2
or a low-K dielectric). In the preferred embodiment, polishing of a structure containing a Cu layer, an underlying Ta barrier layer, and a SiO
2
dielectric layer, using a two-step process is described. In the first step, the Cu overburden is removed while removing minimal amounts of the Ta liner or SiO
2
. The slurry used in the first step of this process is any slurry that can preferentially remove the copper metal overburden covering the semiconductor structure, and has very low rate of material removal on the Ta barrier layer and underlying SiO
2
layer. Typically, this slurry would be alumina based, exhibit an acidic pH, and contain oxidizers that would enhance the chemical-mechanical removal of Cu at accelerated rates (above 2000 A/min). An example of a suitable first-step slurry is presented below.
For the second step, five different methods are described, each method depending on the state of the wafer after the first-step of polishing. The five methods discussed for second-step polishing of Cu interconnect structures can be summarized based on the removal rate and selectivity of each film (Table 1 & 2). It should be noted that the slurries maintaining the selectivities in Table 2 but having different removal rates as described in Table 1 would also be suitable and appropriate in this application.
TABLE 1
Method
Ta RR (A/min)
Cu RR (A/min)
SiO
2
RR (A/min)
1
>1000
>1000
<100
2
Burke Peter A.
Langlois Elizabeth A. (Kegerise)
Pierce Keith G.
Sachan Vikas
Benson Kenneth A.
Biederman Blake T.
Chen Kin-Chan
Rodel Holdings Inc.
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