Patent
1990-09-20
1992-07-07
Carroll, J.
357 34, 357 42, 357 46, 357 59, H01L 2972, H01L 2702, H01L 2904
Patent
active
051287412
ABSTRACT:
An area (7a) on epitaxial layer 2a) is doped negatively (n). A thick oxide layer (16) is grown around an active area of a bipolar transistor (BIP) and field effect transistor (FET). The active area is oxidized to an oxide layer (19) which is coated with a polycrystalline silicon layer (20a). A weak positive LDD doping, is carried out in an area (P) between this silicon layer (20a) and the silicon dioxide layer (16). A heavily negative doping (n+) is carried out on one side of the polycrystalline layer (20a) for constituting emitter (E) of the bipolar transistor (BIP). Its collector consists of the doped epitaxial layer (7a) which is connected to a polycrystalline layer (20c) on the silicon dioxide layer (16). A heavy, positive doping (p+) is carried out on the other side of the polycrystalline layer (20a) to constitute collector/emitter of the (FET), which is connected to the bipolar transistor (BIP) in a Darlington circuit. The method permits the production of a bipolar transistor by itself and also the production of the Darlington circuit.
REFERENCES:
patent: 4110779 (1978-08-01), Rathbone et al.
patent: 4175983 (1979-11-01), Schwabe
patent: 4191585 (1980-03-01), Aomura et al.
patent: 4333774 (1982-06-01), Kamioka
patent: 4400711 (1983-08-01), Avery
patent: 4434543 (1984-03-01), Schwabe et al.
patent: 4445268 (1984-05-01), Hirao
patent: 4486942 (1984-12-01), Hirao
patent: 4507847 (1985-04-01), Sullivan
patent: 4533934 (1985-08-01), Smith
patent: 4558508 (1985-12-01), Kinney et al.
patent: 4590664 (1986-05-01), Prentice et al.
patent: 4613885 (1986-09-01), Haken
patent: 4622738 (1986-11-01), Gwozdz et al.
patent: 4651409 (1987-03-01), Ellsworth et al.
patent: 4654269 (1987-03-01), Lehrer
patent: 4677739 (1987-07-01), Doering et al.
patent: 4694319 (1987-09-01), Kusaka
patent: 4753709 (1988-06-01), Welch et al.
patent: 4769560 (1988-09-01), Tani et al.
patent: 4816423 (1989-03-01), Havemann
patent: 4825274 (1989-04-01), Higuchi et al.
patent: 4830973 (1989-06-01), Mastroianni
patent: 4855244 (1989-08-01), Hutter et al.
patent: 4859630 (1989-08-01), Josquin
patent: 4902640 (1990-02-01), Sachitano et al.
S. M. Sze, Semiconductor Devices Physics and Technology, John Wiley & Sons, New York (1985) p. 211.
"Bipolar Device Incorporated Into CMOS Technolgy," IBM Tech. Disclosure Bulletin, vol. 5, No. 9, Feb. 1986, pp. 3813-3815.
Parrillo et al., "A Verstile High-Performance, Double-Level-Poly Double-Level-Metal, 1.2-Micron CMOS Technology", IEDM, 1986, pp. 244-247.
"Insulated Gate Transistor Modeling and Optimization"; Yilmaz et al, IEEE International Electron Devices Meeting, 1984, pp. 274-277.
"Lightly Doped Drain Structure For Advanced CMOS (Twin-Tub IV)"; Lee et al., IEEE Internation Electron Devices Meeting, 1985, pp. 242-245.
"Process and Device Considerations for Micron and Submicron CMOS Technology"; Parillo, IEEE International Electron Devices Meeting, 1985, pp. 398-402.
Carroll J.
Telefonaktiebolaget L M Ericsson
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