Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-08-02
2011-08-02
Doan, Nghia M (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S100000, C716S101000, C716S102000, C716S106000, C716S107000, C716S116000
Reexamination Certificate
active
07992110
ABSTRACT:
Structured ASIC circuitry that is intended to be functionally equivalent to a programmed block of FPGA circuitry (e.g., a programmed FPGA LUT) is verified for such functional equivalence by using the specification (logical or physical) for the structured ASIC circuitry as a starting point for an FPGA design project. If the design project results in the same FPGA circuitry as it was intended that the structured ASIC circuitry would be functionally equivalent to, the structured ASIC circuitry has been verified and can be added to one or more libraries of structured ASIC modules that are available for use in providing structured ASIC products that are functionally equivalent to programmed FPGA products.
REFERENCES:
patent: 5825202 (1998-10-01), Tavana et al.
patent: 5874834 (1999-02-01), New
patent: 6091262 (2000-07-01), New
patent: 6094065 (2000-07-01), Tavana et al.
patent: 6242945 (2001-06-01), New
patent: 6490707 (2002-12-01), Baxter
patent: 6515509 (2003-02-01), Baxter
patent: 6526563 (2003-02-01), Baxter
patent: 6588006 (2003-07-01), Watkins
patent: 7038490 (2006-05-01), Singh et al.
patent: 7081772 (2006-07-01), Foo
patent: 7157932 (2007-01-01), El-Kik et al.
patent: 7219311 (2007-05-01), Koga et al.
patent: 7243315 (2007-07-01), Tan et al.
patent: 7243329 (2007-07-01), Chua et al.
patent: 7246339 (2007-07-01), Yuan et al.
patent: 7275232 (2007-09-01), Schleicher et al.
patent: 7277902 (2007-10-01), Park et al.
patent: 7348901 (2008-03-01), De Martin et al.
patent: 7360197 (2008-04-01), Schleicher, II et al.
patent: 7363596 (2008-04-01), Park et al.
patent: 7373631 (2008-05-01), Yuan et al.
patent: 2004/0111691 (2004-06-01), Tan et al.
patent: 2004/0261052 (2004-12-01), Perry et al.
patent: 2006/0236292 (2006-10-01), Delp et al.
patent: 2006/0267661 (2006-11-01), Lim et al.
“LCELL WYSIWYG Description for the Stratix II Family,” Version 1.1, Altera Corporation, Mar. 22, 2004.
Park Ji
Yuan Jinyong
Altera Corporation
Doan Nghia M
Ingerman Jeffrey H.
Ropes & Gray LLP
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