Methods of using single spacer to triple line/space frequency

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material

Reexamination Certificate

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Details

C438S585000, C438S595000, C438S671000, C438S947000, C257SE21023, C257SE21027

Reexamination Certificate

active

07871909

ABSTRACT:
Methods for forming patterns having triple the line frequency of a first pattern using only a single spacer are disclosed. For example, the first pattern is formed in a first and a second material using a lithographic process. Sidewall spacers are formed from a third material adjacent to exposed sidewalls of features in the second material. The width of the features in the first pattern in the first material is reduced. For example, the width is reduced to about the target width of features in a final pattern. The width of features in the first pattern in the second material is reduced using remaining portions of the first material as a mask. A second pattern is formed based on remaining portions of the second material and the sidewall spacers. The features in the second pattern may be lines having about ⅓ the width of lines in the first pattern.

REFERENCES:
patent: 6103605 (2000-08-01), Hopper
patent: 6867116 (2005-03-01), Chung
patent: 6955961 (2005-10-01), Chung
patent: 7358140 (2008-04-01), Furukawa et al.
patent: 7611980 (2009-11-01), Wells et al.

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