Methods of testing/stressing a charge trapping device

Details Methods of testing/stressing a charge trapping device Methods of testing/stressing a charge trapping device

2002-12-17

2004-10-19

Pert, Evan (Department: 2829)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

C365S159000

Reexamination Certificate

active

06806117

ABSTRACT:

FIELD OF THE INVENTION
This invention is directed to methods of testing and stressing semiconductor devices, particularly NDR field-effect transistor devices which utilize charge traps that can be altered or re-distributed to improve operational characteristics.
BACKGROUND OF THE INVENTION
Silicon based devices that exhibit a negative differential resistance (NDR) characteristic have long been sought after in the history of semiconductor devices. A new type of CMOS compatible, NDR capable FET is disclosed in the following King et al. applications:
Ser. No. 09/603,101 entitled “A CMOS-PROCESS COMPATIBLE, TUNABLE NDR (NEGATIVE DIFFERENTIAL RESISTANCE) DEVICE AND METHOD OF OPERATING SAME”; and
Ser. No. 09/603,102 entitled “CHARGE TRAPPING DEVICE AND METHOD FOR IMPLEMENTING A TRANSISTOR HAVING A NEGATIVE DIFFERENTIAL RESISTANCE MODE” now issued as U.S. Pat. No. 6,479,862 on Nov. 12, 2002; and
Ser. No. 09/602,658 entitled “CMOS COMPATIBLE PROCESS FOR MAKING A TUNABLE NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE;
all of which were filed Jun. 22, 2000 and which are hereby incorporated by reference as if fully set forth herein. The advantages of such device are well set out in such materials, and are not repeated here.
As also explained in such references, NDR devices can be used in a number of circuit applications, including multiple-valued logic circuits, static memory (SRAM) cells, latches, and oscillators to name a few. The aforementioned King et al. applications describe a break-through advancement that allows NDR devices to be implemented in silicon-based IC technology, using conventional planar processing techniques as for complementary metal-oxide-semiconductor (CMOS) FET devices. The integration of NDR devices with CMOS devices provides a number of benefits for high-density logic and memory circuits.
It is clear, from the advantages presented by the above-described NDR device, that overall improvements in manufacturing, testing and operation of the same are desirable to refine and proliferate such technologies.
In addition, enhancements in trap location control, trap energy level control, and trap formation, are also useful for these types of NDR devices, and could be beneficial to other types of trap-based devices as well.
Furthermore, the prior art to date has been limited generally to devices in which the peak-to-valley ratio (PVR) is not easily adjustable. It would be useful, for example, to be able to control the PVR directly during manufacture, so as to permit a wide variety of NDR behaviors for different circuits on a single die/wafer. Alternatively, the ability to control PVR during normal operation of a device would also be useful, but is generally not possible with current NDR technologies.
SUMMARY OF THE INVENTION
The object of the present invention, therefore, is to address the aforementioned limitations in the prior art, and to provide additional embodiments of trapping devices, NDR devices, and methods of making, operating and testing the same. These and other objects are accomplished by various embodiments of the present invention as described in detail below, it being understood by those skilled in the art that many embodiments of the invention will not use or require all aspects of the invention as described herein.
A first aspect of the invention, therefore, concerns a method of forming a silicon based negative differential resistance (NDR) field effect transistor (FET) comprising the preferred steps of: providing a substrate; forming a first NDR region for the NDR FET over a first portion of the substrate using a first impurity, the first NDR region being adapted for imparting an NDR characteristic to the NDR FET; placing a second impurity in the first portion of the substrate to adjust a threshold voltage characteristic of the NDR FET; performing a first thermal treatment operation for the NDR FET after the above are completed; forming a gate insulating layer for the NDR FET over the first portion of the substrate; performing a second thermal treatment operation for the NDR FET; forming a gate electrode for the NDR FET; forming a source region and a separate drain region for the NDR FET adjacent to the gate electrode, the source region and drain region being coupled through an NDR FET channel located in the first portion of the substrate.
In this manner, an NDR FET preferably operates with a negative differential resistance characteristic when sufficient charge carriers from the channel are temporarily trapped in the first NDR region. The first impurity is preferably a first type dopant, and the second impurity is preferably a second type dopant which is opposite to the first type dopant. The first thermal treatment operation is preferably performed with a furnace, while the second thermal treatment operation is preferably performed with a rapid thermal anneal lamp in a pulsed heated chamber. Furthermore, in addition to the above, a third thermal treatment operation is preferably performed after the gate electrode is formed.
In later steps, a silicide contact to the gate electrode and/or one or both of the source region and the drain region can be formed.
Some embodiments of the invention, therefore, are silicon based negative differential resistance (NDR) field effect transistor (FET) which have a peak-to-valley current ratio (PVR) that exceeds ten (10) over a temperature range of 50° C. In some instances, a PVR can exceed one thousand (1000) over a temperature range of 100° C.
In other embodiments, a silicon on insulator (SOI) substrate is used; a variety of substrates are suitable for the present invention, including strained Si or silicon carbide (SiC).
The impurities added to the FET are used to create charge trapping sites which preferably have an energy characteristic that is higher than a conduction band edge of the substrate.
In other embodiments, an NDR FET and a non-NDR FET are made at the same time using common manufacturing operations. For example, isolation regions, LDD implants, gate insulators, gate electrodes, contacts, source/drain implants, etc., can be done using a shared processing step. In such instances, an NDR region for an NDR device is preferably constructed from a gate insulator region for an NDR FET.
In still other embodiments, two different types of NDR devices can be formed in a common substrate. Thus, a second NDR region for another NDR element is formed over a second region of the semiconductor substrate, the second NDR region being adapted for imparting a second NDR characteristic different from an NDR characteristic for a first NDR FET.
A related aspect of the invention, therefore, pertains to a charge-trap based negative differential resistance (NDR) element which operates with an NDR characteristic defined by a peak current and a valley current. By appropriate distribution of charge traps in a trapping region of the NDR element, including controlling a concentration and energy of the same, a peak-to-valley current ratio (PVR) for the NDR element can be imparted which exceeds ten (10) over a temperature range spanning 50° C.
In other embodiments the PVR can be constructed to vary by less than a factor of five in an operating temperature spanning 25° C. and 125° C. In still other embodiments, the PVR exceeds 1000 in an operating temperature spanning 25° and 125°. The trapping region preferably forms an interface with a channel of a field effect transistor associated with the NDR element.
Other embodiments of charge trapping devices can be similarly constructed to achieve similar performance.
Another aspect of the invention concerns a method of forming a negative differential resistance (NDR) device comprising the steps of: forming a gated silicon-based NDR element; and setting a peak-to-valley ratio (PVR) characteristic of the gated silicon-based NDR element during manufacture of the silicon-based semiconductor transistor to a target PVR value located in a range between a first PVR value and a second PVR value. Thus, a target PVR value can be varied during manufacturing of the NDR device within a semiconductor process su

Affiliated with

Also associated with

Rating

Methods of testing/stressing a charge trapping device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of testing/stressing a charge trapping device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of testing/stressing a charge trapping device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3290964