Methods of redundancy in a floating trap memory element...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S200000

Reexamination Certificate

active

06970383

ABSTRACT:
A method for providing redundancy in a floating charge trap device based programmable logic device includes the steps of sensing for a predetermined amount of stored charge in a first area of a floating trap devices in a floating trap device pair, and sensing for the predetermined amount of stored charge in a second area of the floating trap devices in the floating trap device pair when the charge in the stored charge in the first area in one of the floating trap devices is below the predetermined amount.

REFERENCES:
patent: 4757359 (1988-07-01), Chiao et al.
patent: 5764096 (1998-06-01), Lipp et al.
patent: 5768192 (1998-06-01), Eitan
patent: 5838040 (1998-11-01), Salter, III et al.
patent: 6252273 (2001-06-01), Salter, III et al.
patent: 6356478 (2002-03-01), McCollum
patent: 6816420 (2004-11-01), Liu et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods of redundancy in a floating trap memory element... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of redundancy in a floating trap memory element..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of redundancy in a floating trap memory element... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3474408

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.