Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-05-23
2001-06-12
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185140, C365S185150, C365S185280
Reexamination Certificate
active
06246607
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile memory device, a method of manufacturing the device, and a method of driving the device, and more particularly, to a nonvolatile memory in which the coupling ratio of the memory cells is increased without increasing cell size, through the structure and operation of a “program assist plate,” thereby lowering the operating voltage and increasing the operating speed of the device. The invention may be used in many different types of nonvolatile memory devices, including NAND, NOR, AND, DINOR and other devices.
In a NOR-type electrically erasable programmable read-only memory(EEPROM), two facing memory cells share one bitline contact and one source line, and the memory cells in a row are connected to one bitline. Thus, it is difficult to highly integrate the NOR-type structure, although its high cell current allows it to operate at high speeds.
In a NAND-type structure, two cell strings share one bitline contact and one source line. In one cell string, a plurality of cell transistors are connected in series to the bitline. Accordingly, the NAND-type structure can easily obtain a high level of integration, but it is typically slower than the NOR-type structure due to its low cell current. Because the NAND-type memory cell can be more highly integrated than the NOR-type memory cell, it is generally preferable to employ the NAND-type memory structure for increasing the capacity of a memory device. However, this invention is not limited to application in only NAND type devices
The EEPROM NAND string structure and the basic operation of the NAND-type EEPROM are described below, referring to the accompanying drawings.
FIG. 1
is a plan view showing the layout with respect to one string in a typical NAND-type nonvolatile memory device, and
FIG. 2
is an equivalent circuit diagram of the structure shown in FIG.
1
.
Referring to
FIGS. 1 and 2
, each string of a NAND-type nonvolatile memory device is formed by sequentially connecting a string selection transistor S
1
, a plurality of cell transistors C
1
, . . . , Cn and a source selection transistor S
2
in series between the bitline B/L and a source line S/L in an area represented by a width x and a length y.
FIG. 3A
is a plan view of a transistor cell used in forming each string of the nonvolatile memory device, and
FIG. 3B
is a sectional view taken along line I-I′ of FIG.
3
A.
In
FIG. 3A
, reference numeral
26
indicates a mask pattern for forming an active region, reference numeral
24
indicates a mask pattern for forming a control gate, and reference numeral
22
indicates a mask pattern for forming a floating gate.
Referring to
FIG. 3B
, each transistor cell C
1
, . . . , Cn of
FIG. 1
in the string consists of a floating gate
32
, a control gate
34
and a N-type source/drain
36
, which are sequentially deposited on a P-type semiconductor substrate
30
, with an interdielectric layer inserted therebetween. The programming, erasing and reading of a NAND-type nonvolatile memory device having this structure is described below.
The NAND-type nonvolatile memory is programmed by tunneling an electric charge from a channel region of the cell transistor to the floating gate thereof, to thereby store information. For example, if information is to be programmed or stored in the first transistor cell C
1
, power supply voltage Vcc is applied to the gate of string select transistor S
1
, thereby turning on string select transistor S
1
, and 0V is applied to the gate of source select transistor S
2
, thereby turning off source select transistor. With reference to
FIG. 3B
, a programming voltage Vpgm is applied to the control gate
34
of the first transistor cell C
1
, to thereby generate tunneling. Accordingly, an electric charge in the channel region of the substrate
30
moves to the floating gate
32
, to thereby change the threshold voltage Vth of the first transistor cell C
1
.
After programming, transistor cell C
1
will have (approximately) one of two different threshold voltages depending on the charge transferred to the floating gate
32
. The first and second threshold voltages may correspond to either a “1” or “0” in a two-state memory device. In a multi-state memory device more than two threshold voltages may be used, thereby storing more than one bit per cell.
A read operation is used to determine the programmed state of the NAND memory cell. For example, referring to
FIG. 2
, when reading information stored in the first cell transistor C
1
, the bitline B/L is precharged with a predetermined voltage between approximately 1 V~Vcc. Then, Vcc is applied to each control gate of the string select transistor S
1
, the source select transistor S
2
and unselected cell transistors C
2
, . . . , Cn, (i.e., each cell transistor except for C
1
) to thereby turn-on the transistors. Approximately 0 V is applied to the control gate of the selected first cell transistor C
1
, which is between a first threshold voltage of approximately −3 V when a “1” is stored in the cell and a second threshold voltage of approximately 1V when a “0” is stored in cell C
1
. Thus, if the first cell transistor C
1
is turned on, and a current is sensed between the bitline B/L and source line S/L, the state of the first cell transistor C
1
is determined as “1”. However, if the first cell transistor C
1
is turned off, and no (or very little) current is sensed between the bitline B/L and the source line S/L, the state of the first cell transistor C
1
is determined as “0”. Alternatively, no current could correspond to a “1” and a sensed current could correspond to a “0”.
The erasing operation is performed by tunneling an electric charge from the floating gate
32
to the channel region of the substrate
30
(FIG.
3
B), thereby erasing information stored in the cell. For example, referring to
FIG. 2
, when information is to be erased from the first cell transistor C
1
, the cell string is placed in a floating state by disconnecting it from the bitline B/L and the source line S/L by turning off the string select transistor S
1
and source select transistor S
2
. A voltage of 0V is applied to all
25
wordlines of a selected block of memory cells C
1
, C
2
, . . . Cn. Further, referring to
FIG. 3B
, an erase voltage Verase is applied to the substrate
30
, thereby generating tunneling from the floating gate
32
to the substrate
30
. Thus, the electric charge on the floating gate
32
is moved to the substrate
30
, thereby changing the threshold voltage of the selected memory cells.
In the operation of the nonvolatile memory device described above, a high-voltage of approximately 20V is required to program or erase the memory cells by Fowler-Nordheim (referred to as “F-N”) tunneling. A charge pumping circuit is required to supply a high voltage for programming and erasing, which results in increased chip size and power consumption. Accordingly, in order to increase the density of a nonvolatile memory device, it is important to increase the efficiency of both erasing and programming, and thereby lower the power requirements for Vpgm and Verase.
In order to enhance the operating characteristics without lowering the reliability of the nonvolatile memory device, the capacitance of the structure corresponding to the interdielectric layer deposited between the control gate
34
and the floating gate
32
must be increased, and the program/erase voltage must be lowered. The capacitance may be increased by reducing the thickness of the interdielectric layer or increasing the contact area of the control gate
34
and the floating gate
32
. If the capacitance is increased by reducing the thickness of the interdielectric layer, the data retention capability of the nonvolatile memory device is reduced, and the insulation of the interdielectric layer may be broken during programming and erasing. In addition, the process for producing an interdielectric layer of reduced thickness is difficult. However, a method has recently been developed for increasing the contact area betw
Choi Jung-dal
Mang Kyong-moo
Mai Son
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co.
LandOfFree
Methods of programming nonvolatile memory cells by floating... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of programming nonvolatile memory cells by floating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of programming nonvolatile memory cells by floating... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2540415