Fishing – trapping – and vermin destroying
Patent
1990-04-26
1991-03-19
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 34, 437 41, 437 51, 437 56, 148DIG9, 148DIG10, H01L 21265
Patent
active
050010743
ABSTRACT:
An epitaxial layer (2a) is grown on a substructure (1) of semiconductor material, an area (7a) on said layer being doped negatively (n). A thick oxide layer (16) is grown around an area which is the active area of a bipolar transistor (BIP) and field effect transistor (FET). The active area is oxidized to an oxide layer (19) which is coated with a polycrystalline silicon layer (20a). A weak positive doping, so-called LDD doping, is carried out in an area (P) between this silicon layer (20a) and the silicon dioxide layer (16). A heavily negative doping (n+) is carried out on one side of the polycrystalline layer (20a) for constituting emitter (E) of the bipolar transistor (BIP). Its collector consists of the doped epitaxial layer (7a) which is connected to a polycrystalline layer (20c) on the silicon dioxide layer (16). A heavy, positiv doping (p+) is carried out on the other side of the polycrystalline layer (20a) such as to constitute collector/emitter of the (FET), which is connected to the bipolar transistor (BIP) in a Darlington circuit. The transistors (BIP, FET) are provided with a protective layer of phosphor glass and also with electrical connections. The method permits the production of a bipolar transistor by itself and also the production of the Darlington circuit with a field effect transistor complemental to the field effect transistor (FET).
REFERENCES:
patent: 4434543 (1984-03-01), Schwabe et al.
patent: 4445268 (1984-05-01), Hirao
patent: 4486942 (1984-12-01), Hirao
patent: 4507847 (1985-04-01), Sullivan
patent: 4558508 (1985-12-01), Kinney et al.
patent: 4613885 (1986-09-01), Haker
patent: 4651409 (1987-03-01), Ellsworth et al.
patent: 4677739 (1987-07-01), Doering et al.
patent: 4816423 (1989-03-01), Havemann
patent: 4855244 (1989-08-01), Hutter et al.
patent: 4859630 (1989-08-01), Josquin
"Insulated Gate Transistor Modeling and Optimization"; Yilmaz et al., IEEE International Electron Devices Meeting, 1984, pp. 274-277.
"Lightly Doped Drain Structure For Advanced CMOS (Twin-Tub IV)"; Lee et al., IEEE International Electron Devices Meeting, 1985, pp. 242-245.
"Process and Device Considerations for Micron and Submicron CMOS Technology"; Parillo; IEEE International Electron Devices Meeting, 1985, pp. 398-402.
Hearn Brian E.
Nguyen Tuan
Telefonaktiebolaget L M Ericsson
LandOfFree
Methods of producing on a semi-conductor substructure a bipolar does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of producing on a semi-conductor substructure a bipolar , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of producing on a semi-conductor substructure a bipolar will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2009844