Fishing – trapping – and vermin destroying
Patent
1991-07-25
1993-07-13
Maples, John S.
Fishing, trapping, and vermin destroying
437230, 437189, 437194, 257753, 257765, 257768, 427 98, 427438, H01L 21441, B05D 512
Patent
active
052273326
DESCRIPTION:
BRIEF SUMMARY
This invention relates to methods of plating into holes and to products produced thereby. It is particularly concerned with the manufacture of semiconductor devices and circuits. The invention is more particularly concerned with methods of via-hole filling and with improved semiconductor devices produced using such methods.
Multilevel interconnection technology is indispensable for fabricating complex circuits in semiconductor devices. This involves the creation of via-holes which are subsequently filled. Various methods are known for via-hole filling, but in many cases the reliability is poor.
In one known method of via-hole filling, an electroless nickel plating method is used. An aluminium film is patterned onto a silicon substrate, and a film of phosphosilicate glass (PSG) is deposited on the aluminium pattern as an insulator. Via-holes are formed through the glass film using for example a reactive ion etching method. Then, the bottom surface of the via-hole is activated for subsequent electroless plating using either a "wet" method or a "lift-off" method. In the wet method, the sample is immersed in palladium chloride solution which results in a substitution reaction with only the bottom surface of the via-hole being selectively activated. In the lift-off method on the other hand, palladium is vacuum evaporated in the via-hole so that both the side wall and also the bottom surface of the via-hole are selectively activated. Following either method, electroless nickel plating is carried out in the via-hole. However, these known methods are not wholly satisfactory. With the "wet" method, although a flat surface can generally be obtained for the nickel in the via-hole if the hole is relatively large in diameter, problems arise in the case of small holes. With the lift-off method on the other hand it is difficult to obtain a planar surface at the top of the via-hole.
It is an object of the present invention to provide an improved method of plating, especially for via-hole filling, which has greater reliability and which is particularly suited for electroless plating.
Broadly in accordance with the present invention this is achieved by providing a catalyst within the material to which one wishes to plate, as compared with activating just the surface.
In accordance with the invention there is provided a method of filling a hole of a semiconductor device which comprises depositing on a substrate a body of material which incorporates throughout a catalyst appropriate to a metal subsequently to be plated to the surface thereof, forming an insulation layer on said body, forming a hole through said insulation layer, and depositing the plating metal to fill the hole.
Also in accordance with the invention there is provided a semiconductor device comprising a substrate, a body of material on the substrate which incorporates throughout a catalyst appropriate to a metal to be plated to the surface thereof, an insulation layer on said body having at least one hole therethrough, and a plating metal filling said hole or holes.
It has been found that the incorporation of such a catalyst within the material to which one wishes to plate greatly improves the suitability of the material for subsequent plating, as compared for example with the conventional techniques of activating the bottom surface or the bottom surface and side wall of the hole. One is taking a base material which is not inherently a catalyst and adding something which serves as a catalyst to enable plating to take place.
Preferably, palladium is used as a catalyst, especially for nickel plating, in a concentration appropriate to the particular materials and structure used. However, it is to be understood that materials other than palladium can be used as catalysts, either singly or in combinations.
The film or layer to which one wishes to plate can be any material to which one might wish to plate. Normally this would be a metal or a semiconductor material. Aluminium, aluminium alloys, silicon, aluminium/silicon and titanium are examples of materials which a
REFERENCES:
patent: 3415679 (1968-12-01), Chuss
patent: 4316209 (1982-02-01), Ho et al.
Linden Gerald E.
LSI Logic Corporation
Maples John S.
Rostoker Michael D.
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