Etching a substrate: processes – Planarizing a nonplanar surface
Reexamination Certificate
2001-06-12
2004-05-11
Norton, Nadine G. (Department: 1765)
Etching a substrate: processes
Planarizing a nonplanar surface
C216S088000, C216S089000, C438S692000, C438S693000, C252S079300
Reexamination Certificate
active
06733685
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods of planarizing structures on wafers and substrates which employ a polish-stop layer in a polishing process, such as standard mechanical polishing and chemical-mechanical polishing (CMP). As exemplary applications, the methods may be used to form a plurality of structures having uniform height, and multi-layer interconnect substrates for multi-chip modules.
BACKGROUND OF THE INVENTION
In standard polishing processes, the wafer surface is pressed against a polishing pad which is coated with a slurry containing a fine abrasive, such as silica. The polishing pad is usually flat, and the abrasive is held by the pores of the pad and mechanically scrapes away the high points of the wafer. In chemical-mechanical polishing (CMP), an acid or base is added to the slurry, which preferentially etches one or more of the materials to be removed. In some cases, the acid or base converts the material to be removed to a different form which is more readily removed by the abrasive.
In recent years, chemical-mechanical polishing has received more attention and played a more important role in the fabrication of microelectronic devices, mainly because of its capability of providing good global planarity, as well as good local planarity. If planarization processes are not applied in the device fabrication, the interconnect layers are typically finished with varying degrees of non-planarity. Such topography makes it difficult for the fabrication of the next layer. For example, a photoresist layer formed over a highly non-planar surface will not have a uniform thickness, which will lead to non-uniformity in the patterning of the resist. In the case of stacked patterns, this obstacle becomes even more prominent when such non-planarity is imprinted or amplified into the next layer, and the cumulative non-planarity may become so severe after just a few layers that the photolithography process becomes a limiting factor in the device fabrication. CMP processes, such as oxide and metal polishing, have been employed in the manufacturing of integrated circuit (IC) chips, but not so much in chip packaging.
While standard polishing and chemical-mechanical polishing processes can greatly improve planarity of a wafer, the processes do have particular drawbacks. For example, large areas of the wafer having relatively soft, easily abraded material can be over-etched (so-called “dishing”). Also, it is often difficult to control the endpoint of the processes in order to produce layers having known thicknesses. The present invention is directed to addressing these drawbacks.
SUMMARY OF THE INVENTION
The present invention encompasses methods of planarizing structures formed on the surfaces of substrates and wafers. Broadly stated, the present invention forms a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is then formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing or chemical-mechanical polishing.
With the methods according to the present invention, a substantially planar polish-stop layer is achieved with a high polishing contrast between the field area of the polish-stop layer and the structures to be planarized. (The field area is generally the area which is between the structures and which is substantially within the same plane.) Polishing time is thereby minimized, and dishing is consequently minimized. Moreover, the thickness of the planarizing layer in the low areas can be set with a high degree of precision, which enables the methods of the present invention to be used to construct structures of relatively precise and uniform height.
In one embodiment of the present invention, the polish-stop layer is formed having apertures around corresponding structures, rather thin being formed uniformly across the substrate. The apertures increase the polishing contrast between tops of the structures and the field area of the polish-stop layer since there is no polish-stop material over the tops of the structures before the structures are polished.
In another embodiment of the present invention, the fabrication of the structures is integrated with the formation of the planarization layer and polish-stop layer. In this embodiment, the planarization layer is first formed before the structures are formed. The polish-stop layer is then formed over the planarization layer, and a second planarizing layer, preferably a photoresist layer, is formed over the polish-stop layer. These three layers collectively comprise a composite layer. To form the structures, apertures are formed through the composite layer, and are filled with material to a point above the level of the polish-stop layer. The second planarizing layer is removed, leaving the tops of the structures extending above the top of the polish-stop layer. The resulting structure, which has a high polishing contrast, is subsequently polished. Since the polish-stop layer is generally thin in comparison to thickness of the second planarizing layer, the polish-stop layer may be pre-patterned with apertures for the structures before the second planarizing layer is formed over the substrate.
The methods according to the present invention may be used to construct multilevel interconnect substrates which have dielectric layers of precise and uniform thicknesses. As is known in the multi-chip module art, such a dielectric layer is positioned between two layers of metal interconnect and has a number of conductive vias running through it which connect metal interconnect lines between the two metal layers. Because of the particular steps of the prior art construction methods, the tops of the vias in prior art multi-chip modules (MCM's) dip below the top of the dielectric layer in which they are formed, thereby creating a non-uniform surface. As the number of these dielectric and metal layers increases in the structure, some of the non-uniformities add constructively to produce a final top layer whose surface is highly non-uniform.
A fabrication method according to the present invention may be used to prevent such non-uniform surfaces. In this method, a relatively thick layer of photoresist material, or the like, is formed over a metal layer, the thickness being greater than that of the dielectric layer that will ultimately be formed. The photoresist layer is exposed and developed to form apertures therein, which are then filled with conductive material to form conductive posts (or other conductive structures). The photoresist is thereafter removed to expose the posts and the starting metal layer. A material, usually a dielectric material, is then coated over the posts and the starting metal layer according to the present invention such that the top surface of the material layer has high areas over the posts, low areas between the posts, and transition areas between the high and low areas, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is then formed over at least the low areas of the material layer, the polish-stop layer being more resistant to polishing than the material. The resulting surface is then polished to the level of the polish-stop layer, which is thereafter removed. A second metal layer may then be formed over the planarized material layer, and the sequence may be repeated to form one or more additional material layers. This embodiment of the present invention is opposite to convention via formation practices in that the conductive material of the via is formed before the aperture is formed in the material layer (e.g., dielectric layer). T
Beilin Solomon I.
Chou William T.
Lee Michael G.
Moresco Larry Louis
Wang Wen-chou Vincent
Ahmed Shamim
Fujitsu Limited
Norton Nadine G.
Sheppard Mullin Richter & Hampton LLP
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