Semiconductor device manufacturing: process – Forming schottky junction – Compound semiconductor
Reexamination Certificate
2000-05-22
2001-09-25
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Forming schottky junction
Compound semiconductor
C438S574000, C438S605000, C438S606000, C438S167000, C438S172000
Reexamination Certificate
active
06294446
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high electron mobility transistor for use in a radio-frequency amplifier which operates in a millimeter wave band, and a method of manufacturing such a high electron mobility transistor and a field-effect transistor.
2. Description of the Prior Art
There has been developed a high electron mobility transistor which has a channel layer of high electron mobility (aluminum gallium arsenide) for improved radio-frequency characteristics. In the developed high electron mobility transistor, a thin layer of InGaAs is formed intermediate in a wide-band gap layer of high-resistance AlGaAs (aluminum gallium arsenide), thereby producing a channel layer of double heterojunction structure. Electrons are supplied at a relatively high concentration into the channel layer from silicon-doped planar layers that are disposed respectively in upper and lower wide-band gap layer portions.
U.S. patent application Ser. No. 08/565,295 filed Nov. 30, 1995, entitled “FIELD-EFFECT TRANSISTOR” and assigned to the present assignee, discloses a high-performance high electron mobility transistor whose mutual conductance changes to a small degree with respect to a gate voltage. because the thickness of the channel layer is limited to a value small enough to regard an electron gas layer as a substantially single layer and the upper and lower wide-band gap layer portions of AlGaAs have a high resistance.
If the channel layer is thick, the electron gas layer formed in the channel layer is localized in the vicinity of the heterojunction plane, and hence separated into two layers whose depths from the transistor surface are different from each other, i.e., whose distances from the gate electrode are different from each other. The gate voltage has different effects on two electron (gas layers which are separated at different depths, i.e., spaced different distances from the gate electrode. As a consequence, the mutual conductance becomes largely dependent on the gate voltage.
According to the invention disclosed in U.S. patent application Ser. No. 08/565295 referred to above, the thickness of the channel layer is limited to a value small enough to regard an electron gas layer as a substantially single layer, specifically to a thickness in the range of from 50 Åto 150 Å, and the upper and lower layers of AlGaAs disposed adjacent to the thin channel layer have a high resistance. The upper and lower layers of AlGaAs above and below the thin channel layer have a high resistance because as the resistance of the upper and lower layers of AlGaAs increases, the gate voltage affects a wider area including the channel layer, resulting in the same effect as caused by.a reduction in the thickness of the channel layer.
FIG. 1
of the accompanying drawings schematically shows the structure of the high electron mobility transistor disclosed in U.S. patent application Ser. No. 08/565,295 referred to above. As shown in
FIG. 1
, the high electron mobility transistor has a semi-insulating GaAs substrate
31
, a super-lattice buffer layer
32
disposed on the semi-insulating GaAs substrate
31
for preventing an unwanted carrier from leaking, a pair of lower and upper wide-band gap layers
33
,
35
of AlGaAs disposed on the super-lattice buffer layer
32
, an InGaAs channel layer
34
disposed between the lower and upper wide-band gap layers
33
,
35
, a pair of silicon-doped planar layers
33
a
,
35
a
disposed respectively in the lower and upper wide-band gap layers
33
,
35
, an n
+
GaAs contact layer
36
disposed on the upper wide-band gap layer
35
, an SiO
2
film
37
disposed on the n
+
GaAs contact layer
365
, a passivation film
38
disposed on the SiO
2
film
37
, and a gate electrode
39
of T-shaped cross section disposed on the upper wide-band gap layer
35
and covered with the passivation film
38
.
The channel layer
34
has a thickness which is selected to be of a value small enough to cause electron gases, which would otherwise be localized in the vicinity of heterojunctions formed between the channel layer
34
and the lower and upper wide-band gap layers
33
,
35
and hence tend to be separated from each other, to be combined into a single electron gas layer that is controllable depending on changes in the gate electrode. Specifically, the thickness of the channel layer
34
is in the range of from 50 Å to 150 Å.
FIG. 2
of the accompanying drawings shows experimental data on electric characteristics of the high electron mobility transistor shown in FIG.
1
. The electric characteristics shown in
FIG. 2
represent the relationship between the drain voltage and the drain current at various discrete values of the gate voltage. It can be seen from
FIG. 2
that the drain current increases substantially uniformly as the gate voltage increases and the mutual conductance does not vary greatly depending on the gate electrode.
FIG. 3
of the accompanying drawings shows experimental data on the relationship between the mutual conductance and the gate voltage of the high electron mobility transistor or field-effect transistor (FET) shown in
FIG. 1
, a conventional high electron mobility transistor or FET, and an improved conventional high electron mobility transistor or FET. The graph shown in
FIG. 3
has a vertical axis indicative of the mutual conductance (gm) per unit gate width and a horizontal axis indicative of the gate voltage (V). In
FIG. 3
, the solid-line curve A represents the experimental data of the high electron mobility transistor shown in
FIG. 1
, the broken-line curve B represents the experimental data of the conventional high electron mobility transistor, and the dot-and-dash-line curve C represents the experimental data of the improved conventional high electron mobility transistor. The experimental results illustrated in
FIG. 3
clearly shows justifying support for the advantages of the, high electron mobility transistor disclosed in U.S. patent application Ser. No. 08/565,295.
U.S. patent application Ser. No. 08/558,548 filed Nov. 15, 1995 discloses a method of manufacturing a semiconductor device, which is suitable for the manufacture of the high electron mobility transistor shown in FIG.
1
. According to the disclosed method, an etching solution suitable for a selective wet etching process for forming a recess in which a gate electrode will be formed comprises a mixture of ammonia water and hydrogen peroxide water mixed at a ratio of 1 to 4000 or more and diluted by water.
In the high electron mobility transistor shown in
FIG. 1
, the entire surface of the T-shaped gate electrode
39
is covered with the passivation film
38
. The passivation film
38
comprises an SiO
2
/N film or the like having a large dielectric constant which is several times the dielectric constant of air. Therefore, the parasitic capacitance of the gate electrode
39
is so large that the high electron mobility transistor has poor radio-frecluency characteristics.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a high electron mobility transistor which has a low gate parasitic capacitance for improved radiofrequency characteristics.
To achieve the above object, there is provided in accordance with the present invention a high electron mobility transistor comprising a channel layer for developing therein an electron gas layer having a substantially uniform electron gas density, upper and lower high-resistance wide-band gap layers disposed respective over and beneath the channel layer, each of the upper and lower high-resistance wide-band gap layers having a silicon-doped planar layer disposed therein, a contact layer disposed on the upper wide-band gap layer for contact with source and drain electrodes, the contact layer having a recess defined therein which divides the contact layer, a gate electrode of substantially T-shaped cross section disposed in the recess, and a passivation film disposed on an inner wall surface of the recess and a lower portion
Bowers Charles
Honda Giken Kogyo Kabushiki Kaisha
Lyon & Lyon LLP
Smoot Stephen W.
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