Methods of making self-aligned power MOSFET with integral source

Details Methods of making self-aligned power MOSFET with integral source Methods of making self-aligned power MOSFET with integral source

1985-01-22

1986-07-08

Ozaki, George T.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29580, 29591, 148177, 148187, 357 234, H01L 2140

Patent

active

045984611

ABSTRACT:
Double diffused power MOSFET's and methods of manufacture. The source, base and drain regions of a double diffused power MOSFET correspond respectively to the emitter, base and collector of a parasitic bipolar transistor. Double diffused power MOSFET's perform better when provided with an ohmic short between the source and base regions to prevent turn-on of the parasitic bipolar transistor. In one form of ohmic short between the base and source regions, the source terminal comprises a metallic electrode, preferably aluminum, deposited over the source region, and the ohmic short comprises at least one microalloy spike extending from the source terminal metallic electrode through the source region and partly into the base region. Such microalloy spikes are formed by heating the semiconductor substrate after the metallic electrode has been deposited under appropriate conditions. In another form, a V-groove is formed by preferential etching in the source and base regions. In particular the V-groove extends through the source region, with the bottom of the V-groove extending only partly into the base region. A metallic source electrode is deposited over the source region and into the V-groove in ohmic contact with both the source and base regions to form both the source terminal and the ohmic short. These two forms of ohmic short are integral in nature, and facilitate an overall MOSFET structure and manufacturing process characterized by a minimum number of masking steps, self-alignment, and increased active device area.

REFERENCES:
patent: 3845495 (1974-10-01), Cauge et al.
patent: 3988761 (1976-10-01), Kanazawa
patent: 4181542 (1980-01-01), Yoshida et al.
patent: 4219835 (1980-08-01), van Loon et al.
patent: 4271424 (1981-06-01), Inayoshi
patent: 4344081 (1982-08-01), Pao et al.
patent: 4345265 (1982-08-01), Blanchard
patent: 4417385 (1983-11-01), Temple
patent: 4430792 (1984-02-01), Temple
patent: 4443931 (1984-04-01), Baliga et al.
patent: 4466176 (1984-08-01), Temple
patent: 4516143 (1985-05-01), Love
Kendall, Applied Physics Letters, "On Etching Very Narrow Grooves in Silicon", vol. 26, No. 4, Feb. 15, 1975, pp. 195-198.

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