Methods of making magnetoresistive memory devices

Details Methods of making magnetoresistive memory devices Methods of making magnetoresistive memory devices

2001-10-04

2003-12-02

Alanko, Anita (Department: 1765)

Etching a substrate: processes

Forming or treating article containing magnetically...

C216S038000, C216S041000, C216S067000, C216S075000, C216S088000, C216S100000, C204S192340

Reexamination Certificate

active

06656372

ABSTRACT:

TECHNICAL FIELD
The invention pertains to methods of making magnetoresistive memory devices, such as, for example, magnetic random access memory (MRAM) devices.
BACKGROUND OF THE INVENTION
Numerous types of digital memories are utilized in computer system components, digital processing systems, and other applications for storing and retrieving data. MRAM is a type of digital memory in which digital bits of information comprise alternative states of magnetization of magnetic materials in memory cells. The magnetic materials can be thin ferromagnetic films. Information can be stored and retrieved from the memory devices by inductive sensing to determine a magnetization state of the devices, or by magnetoresistive sensing of the magnetization states of the memory devices. It is noted that the term “magnetoresistive device” characterizes the device and not the access method, and accordingly a magnetoresistive device can be accessed by, for example, either inductive sensing or magnetoresistive sensing methodologies.
A significant amount of research is currently being invested in magnetic digital memories, such as, for example, MRAMs, because such memories are seen to have significant potential advantages relative to the dynamic random access memory (DRAM) components and static random access memory (SRAM) components that are presently in widespread use. For instance, a problem with DRAM is that it relies on power storage within capacitors. Such capacitors leak energy, and must be refreshed at approximately 15 nanosecond intervals. The constant refreshing of DRAM devices can drain energy from batteries utilized to power the devices, and can lead to problems with lost data since information stored in the DRAM devices is lost when power to the devices is shut down.
SRAM devices can avoid some of the problems associated with DRAM devices, in that SRAM devices do not require constant refreshing. Further, SRAM devices are typically faster than DRAM devices. However, SRAM devices take up more semiconductor real estate than do DRAM devices. As continuing efforts are made to increase the density of memory devices, semiconductor real estate becomes increasingly valuable. Accordingly, SRAM technologies are difficult to incorporate as standard memory devices in memory arrays.
MRAM devices have the potential to alleviate the problems associated with DRAM devices and SRAM devices. Specifically, MRAM devices do not require constant refreshing, but instead store data in stable magnetic states. Further, the data stored in MRAM devices can potentially remain within the devices even if power to the devices is shutdown or lost. Additionally, MRAM devices can potentially be formed to utilize less than or equal to the amount of semiconductor real estate associated with DRAM devices, and can accordingly potentially be more economical to incorporate into large memory arrays than are SRAM devices.
Although MRAM devices have potential to be utilized as digital memory devices, they are currently not widely utilized. Several problems associated with MRAM technologies remain to be addressed.
Exemplary problems associated with prior art processing are described with reference to
FIGS. 1 and 2
.
FIG. 1
illustrates a wafer fragment
10
comprising a semiconductor substrate
12
. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
A stack
14
is provided over substrate
12
, and will ultimately be utilized to form an MRAM device. Stack
14
comprises a conductive material
16
, a first barrier layer
18
, a first magnetic material
20
, a non-magnetic material
22
, a second magnetic material
24
, and a second barrier layer
26
. It is noted that the shown layers are those pertinent to the present invention, and that the layers can be formed physically against one another as shown, or other layers (not shown) can be provided between various of the shown layers in forming an MRAM construction.
Conductive material
16
can comprise, for example, either elemental copper or copper alloys.
Layers
18
and
26
are referred to as barrier layers to indicate that layers
18
and
26
can impede diffusional exchange of materials across the layers. Layers
18
and
26
can alternatively be referred to as spacer layers, or as anti-magnetic layers. Layers
18
and
26
can comprise, for example, elemental tantalum or tantalum nitride (TaN). Layers
18
and
26
can comprise other components in addition to, or alternatively to, tantalum-containing components, such as, for example, Ti, W, TiN, SiN, or SiO
2
. Layers
18
and
26
can comprise the same compositions as one another, or different compositions.
Magnetic layers
20
and
24
can comprise, for example, one or more of nickel, iron, cobalt, iridium, platinum, ruthenium, and manganese. Layers
20
and
24
can comprise the same compositions as one another, or different compositions. After layers
20
and
24
are incorporated into an MRAM device, one of the magnetic layers
20
and
24
will typically be referred to as a sense layer and the other will be referred to as a reference or pinned layer. Another magnetic layer (not shown) can be provided proximate the reference layer to pin the layer into a particular magnetic orientation.
Non-magnetic layer
22
can comprise either an electrically conductive material (for example, in applications in which the resultant MRAM is to be a giant magnetoresistive (GMR) device), or alternatively can comprise electrically insulative material (for example, in applications in which a resulting MRAM device is to be a tunnel magnetoresistive (TMR) device). Exemplary conductive materials which can be utilized for non-magnetic layer
22
are copper and copper alloys; and exemplary insulative materials which can be utilized for non-magnetic layer
22
are aluminum oxide (Al
2
O
3
), silicon oxynitride (Si
x
N
y
O
z
, wherein x, y and z are greater than 0) and silicon dioxide (SiO
2
).
A masking block
30
is shown formed over stack
14
. Masking block
30
can comprise photoresist, and can be formed utilizing photolithographic patterning methodologies. Block
30
can further comprise a so-called hard mask alternatively to, or in addition to, a photoresist block. The block
30
is in a shape comprising a desired peripheral pattern. The peripheral pattern is defined by the location of sidewall peripheries
32
and
34
of the masking block.
Referring to
FIG. 2
, the peripheral pattern of block
30
is transferred to underlying layers
18
,
20
,
22
,
24
and
26
with a suitable etch to extend the peripheral pattern of block
30
through layers
18
,
20
,
22
,
24
and
26
. The etched layers
18
,
20
,
22
,
24
and
26
define an MRAM construction
50
. The etch utilized for etching through layers
18
,
20
,
22
,
24
and
26
can comprise a primarily physical etch (as opposed to a primarily chemical etching process), such as, for example, ion milling or some of the reactive ion etching processes.
The etching of layers
18
,
20
,
22
,
24
and
26
forms sputtered material
40
as a reaction by-product, and some of the sputtered material deposits on sidewalls of the patterned layers. Sputtered material
40
comprises magnetic components from layers
20
and
24
, and accordingly can magnetically interconnect layers
20
and
24
across an outer sidewall of non-magnetic layer
22
. Such magnetic interconnection of layers
20
and
24
can render a resultant MRAM device comprising layers
20
and
24
inoperative. Specifically, it is desired that layers
20
and
24
be isolated from one another during opera

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