Semiconductor device manufacturing: process – Chemical etching – Altering etchability of substrate region by compositional or...
Reexamination Certificate
1997-03-14
2001-10-30
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Altering etchability of substrate region by compositional or...
C216S038000, C216S087000, C257S306000, C438S692000, C438S753000
Reexamination Certificate
active
06309975
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to methods of patterning a volume of silicon-containing material on a semiconductor substrate. More particularly, the present invention relates to methods of forming shaped structures from a volume of silicon-containing material on a semiconductor substrate using ion implantation and an etching process which is selective to either implanted silicon-containing material or to unimplanted silicon-containing material. The present invention is particularly useful for forming shaped silicon-containing material structures such as polysilicon plugs, interconnect lines, transistor gates, trenches, and capacitor storage nodes in an efficient manner and with a high degree of control over the resulting profile of the shaped structure.
2. The Relevant Technology
In the context of this document, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term “substrate” refers to any supporting structure including but not limited to the semiconductor substrates described above.
Integrated circuits on electronic chips provide the logic and memory of computers and other intelligent electronic devices. These integrated circuits have advanced to a highly functional level to the benefit of the computers and other intelligent electronic devices. The vast functionality of integrated circuits is also being provided at a cost that is economical, allowing the computers and intelligent electronic devices to be provided to consumers at affordable prices. Integrated circuits are currently manufactured by an elaborate process in which semiconductor devices, insulating films, and patterned conducting films are sequentially constructed in a predetermined arrangement on a semiconductor substrate. The conventional semiconductor devices which are formed on the semiconductor wafer include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of these semiconductor devices are formed on a single semiconductor wafer.
The computer and electronics industry is constantly under market demand to increase the speed and functionality and to reduce the cost of integrated circuits. One manner of accomplishing this task is by increasing the density with which the semiconductor devices can be formed on a given surface area of a semiconductor wafer. In order to do so, the semiconductor devices must be decreased in dimension in a process known as miniaturization. The challenge in miniaturizing integrated circuits is to do so without greatly increasing the cost of the processes by which integrated circuits are manufactured.
Accordingly, one aspect of integrated circuit manufacturing that is in need of improvement is the complexity of the processes by which integrated circuits are manufactured. As integrated circuits have become increasingly complex, processing steps for forming the integrated circuits have multiplied in length. The number of fabrication process steps has also increased in proportion to the increased complexity of the integrated circuits. It is axiomatic that, as integrated circuit manufacturing processes increase in complexity, the cost of production of the integrated circuits correspondingly increases. Accordingly, in order to maintain an affordable cost of production of the improved and more functional computers and other intelligent electronic devices, new methods for manufacturing integrated circuits are needed which are simpler and more efficient, which assist in the miniaturization process, and which do not compromise integrated circuit quality or performance.
One necessary stage of conventional integrated circuit manufacturing processes is the formation of shaped structures which are used to form the semiconductor devices or discrete features of the semiconductor devices, such as MOS transistor gate regions and capacitor storage nodes. These shaped structures are generally formed by the patterning of structural layers on the semiconductor wafer. The structural layers are typically patterned with a process which includes depositing the structural layer, covering the structural layer with a photoresist mask, and etching away portions of the structural layer that are not covered by the photoresist mask. The portion or portions of the structural layer that are covered by the photoresist mask form the shaped structure.
The photoresist mask through which the structural layer is etched is conventionally formed by a process known as photolithography. Photolithography generally utilizes a beam of light, such as ultraviolet (UV) light, to transfer a pattern through an imaging lens from a photolithographic template to a photoresist coating which has been applied to the structural layer being patterned. The pattern of the photolithographic template includes opaque and transparent regions with selected shapes that match corresponding openings and intact portions intended to be formed into the photoresist coating. The photolithographic template is conventionally designed by computer assisted drafting and is of a much larger size than the section of the semiconductor wafer on which the photoresist coating is to be exposed. Light is passed through the photolithographic template and is focused on the photoresist coating in a manner that reduces the pattern of the photolithographic template to the required size on the wafer. For positive photoresist the portions of the photoresist coating that are unmasked are developed away.
The resolution with which a pattern can be transferred to the photoresist coating from the photolithographic template place limits upon feature sizes that can be created. The dimensions of the openings and intact regions of the photoresist mask, and consequently the dimensions of the shaped structures that are formed with the use of the photoresist mask, are correspondingly limited. Photolithographic resolution limits are thus a barrier to further miniaturization of integrated circuits. Accordingly, a need exists for an improved method of forming shaped structures having feature sizes smaller than 0.2 microns.
As an example of one such shaped structure which is in need of being formed with reduced size is an ovonic cell of a programmable resistor. An ovonic cell is a region of chalcogenide material that has a resistance which is programmable by an electrical charge passed through the ovonic cell. Generally, the ovonic cell is formed by etching out an opening from a volume of material, and thereafter depositing the chalcogenide material into the opening. As a high charge density is most suitable for programming the ovonic cell, it is desirable that the opening be formed with a small cross-sectional area, which serves to increase the density of a charge applied thereto. The opening is conventionally patterned with photolithography. It would be desirable to find a commercially feasible method of forming the opening with a width narrower than about 0.2 microns.
Certain alternative methods to photolithography for forming shaped structures of semiconductor devices with higher resolution than is possible with photolithography do currently exist, but these alternative methods have certain drawbacks and limitations which keep them from being widely employed. For example, one such alternative method is referred to as a disposable spacer flow process. The disposable spacer flow process involves initially forming a sacrificial block of material and then forming spacers at the edges of the sacrificial block of material. The sacrificial block of material is situated such that the spacers are formed in the locations where resulting high resolution shaped structures are to be located. Once the spacers are formed, the sacrificial block of material is remove
Figura Thomas A.
Li Li
Ma Kin F.
Pan Pai-Hung
Parekh Kunal R.
Micro)n Technology, Inc.
Powell William
Workman & Nydegger & Seeley
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