Methods of maintaining cache coherence and processor synchroniza

Details Methods of maintaining cache coherence and processor synchroniza Methods of maintaining cache coherence and processor synchroniza

1989-03-01

1994-01-04

Lee, Thomas C.

Boots, shoes, and leggings

395200, 395650, 364DIG1, 3642281, 3642283, 3642292, 3642303, 3642304, 3642401, 36424344, 3642461, 3642592, 3642707, G06F 1212, G06F 1516

Patent

active

052768287

ABSTRACT:
For use with a multiprocessor system employing shared memory, a software controlled method maintains cache coherency and execution synchronization among processors. A processor executing a SEND instruction transfers a cache line to one or more processors executing a RECEIVE instruction in a synchronized manner. The processors also execute the SEND and RECEIVE instructions to synchronize the execution of iterations of a program loop whereby a control processor distributes indices of the iterations to be performed by each worker processor.

REFERENCES:
patent: 3810114 (1974-05-01), Yamada et al.
patent: 3813651 (1974-05-01), Yamada
patent: 4866664 (1989-09-01), Burkhardt, Jr. et al.
patent: 4965717 (1990-10-01), Cutts, Jr. et al.
patent: 4984153 (1991-01-01), Kregness et al.
patent: 4989131 (1991-01-01), Stone
patent: 5025365 (1991-06-01), Mathur et al.
patent: 5041971 (1991-08-01), Carvey et al.
patent: 5045996 (1991-09-01), Barth et al.

Affiliated with

Also associated with

Rating

Methods of maintaining cache coherence and processor synchroniza does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of maintaining cache coherence and processor synchroniza, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of maintaining cache coherence and processor synchroniza will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-314979