Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2008-01-01
2008-01-01
Frejd, Russell (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C714S738000, C716S030000, C716S030000
Reexamination Certificate
active
10430588
ABSTRACT:
Methods of reducing the amount of logic in a digital circuit without affecting the functionality of the circuit. A circuit description and one or more test patterns are supplied to a fault simulator. The fault simulator runs the test patterns on the circuit, and identifies any nodes that did not transition in either direction (“non-transitioning nodes”). If the test patterns provide full coverage of the desired functionality for the circuit, each of the non-transitioning nodes is unnecessary to the logical functionality of the circuit in the target application. Therefore, the logic driving the non-transitioning nodes is removed from the circuit. The modified circuit can then be re-simulated, if desired, to verify that the relevant functionality of the circuit has not changed.
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Cartier Lois D.
Frejd Russell
Xilinx , Inc.
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