Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2005-06-07
2005-06-07
Thai, Luan (Department: 2829)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S424000, C438S697000
Reexamination Certificate
active
06902984
ABSTRACT:
In one aspect, the invention includes a method of forming a void region associated with a substrate, comprising: a) providing a substrate; b) forming a sacrificial mass over the substrate; c) subjecting the mass to hydrogen to convert a component of the mass to a volatile form; and d) volatilizing the volatile form of the component from the mass to leave a void region associated with the substrate. In another aspect, the invention includes a method of forming a capacitor construction, comprising: a) forming a first capacitor electrode over a substrate; b) forming a sacrificial material proximate the first capacitor electrode; c) forming a second capacitor electrode proximate the sacrificial material, the second capacitor electrode being separated from the first capacitor electrode by the sacrificial material, at least one of the first and second electrodes being a metal-comprising layer; and d) subjecting the sacrificial material to conditions which transport a component from the sacrificial material to the metal-comprising layer, the transported component leaving a void region between the first and second capacitor electrodes.
REFERENCES:
patent: 3954523 (1976-05-01), Magdo et al.
patent: 5023200 (1991-06-01), Blewer et al.
patent: 5273616 (1993-12-01), Bozler et al.
patent: 5461003 (1995-10-01), Havemann et al.
patent: 5470801 (1995-11-01), Kapoor et al.
patent: 5707896 (1998-01-01), Chiang et al.
patent: 5731241 (1998-03-01), Jang et al.
patent: 5753548 (1998-05-01), Yu et al.
patent: 5783253 (1998-07-01), Roh
patent: 5885900 (1999-03-01), Schwartz
patent: 5989776 (1999-11-01), Felter et al.
patent: 6140200 (2000-10-01), Eldridge
patent: 6333556 (2001-12-01), Juengling
Togo, M., “A Gate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs”, 1996 Sympos. On VLSI Technology Digest of Technical Papers, IEEE 1996, pp. 38-39.
Anand, M.B., “NURA: A Feasible, Gas-Dielectric Interconnect Process”, 1996 Symposium on VLSI Technology Digest of Technical Papers, IEEE 1996, pp. 82-83.
Watanabe, H., “A Novel Stacked Capacitor with Porous-Si Electrodes for High Density DRAMs”, Micro-Electronics Research Laboratories, NEC Corp, pp. 17-18.
ABSTRACT: Anderson, R.C. et al., “Porous Polycrystalline Silicon: A New Material for MEMS”, Journal of Microelectromechanical Systems (Mar. 1994), vol. 3, No. 1, pp. 10-18.
M. B. Anand, “Use of Gas as Low-κ Interlayer Dielectric in LSI's: Demonstration of Feasibility”, IEEE Transactions on Electron Devices, vol. 44, No. 11, Nov. 1997, pp. 1965-1971.
Micro)n Technology, Inc.
Thai Luan
Wells St. John P.S.
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