Methods of forming trench isolated integrated circuit...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S424000, C438S435000

Reexamination Certificate

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06939780

ABSTRACT:
Trench isolated integrated circuit devices are fabricated by forming a trench including sidewalls in an integrated circuit substrate, and forming a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is formed on the lower device isolation layer and in the grooves. Trench isolated integrated circuit devices include an integrated circuit substrate including a trench having sidewalls and a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is provided on the lower device isolation layer and in the grooves.

REFERENCES:
patent: 6093600 (2000-07-01), Chen et al.
patent: 6265302 (2001-07-01), Lim et al.
patent: 6531377 (2003-03-01), Knorr et al.
patent: 6624464 (2003-09-01), Shin et al.
patent: 6750117 (2004-06-01), Hung et al.
patent: 2002-0074716 (2002-10-01), None
Notice to File a Response/Amendment to the Examination Report, Korean App. No. 10-2002-0061720, Jul. 19, 2004.

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