Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2005-09-06
2005-09-06
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S435000
Reexamination Certificate
active
06939780
ABSTRACT:
Trench isolated integrated circuit devices are fabricated by forming a trench including sidewalls in an integrated circuit substrate, and forming a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is formed on the lower device isolation layer and in the grooves. Trench isolated integrated circuit devices include an integrated circuit substrate including a trench having sidewalls and a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is provided on the lower device isolation layer and in the grooves.
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patent: 2002-0074716 (2002-10-01), None
Notice to File a Response/Amendment to the Examination Report, Korean App. No. 10-2002-0061720, Jul. 19, 2004.
Shin Jin-Hyun
Yun Jae-Sun
Myers Bigel & Sibley & Sajovec
Perkins Pamela
Zarabian Amir
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