Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
2000-02-02
2004-05-18
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S391000, C438S221000, C438S294000, C438S295000, C438S296000, C438S680000, C438S424000
Reexamination Certificate
active
06737328
ABSTRACT:
TECHNICAL FIELD
The invention pertains to methods of forming silicon dioxide layers, such as, for example, methods of forming trench isolation regions.
BACKGROUND OF THE INVENTION
Integrated circuitry is typically fabricated on and within semiconductor substrates, such as bulk monocrystalline silicon wafers. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrates” refers, to any supporting structure including, but not limited to, the semiconductive substrates described above.
Electrical components fabricated on substrates, and particularly bulk semiconductor wafers, are isolated from adjacent devices by insulating materials, such as silicon dioxide. One isolation technique uses shallow trench isolation, whereby trenches are cut into a substrate and are subsequently filled with an insulating material, such as, for example, silicon dioxide. In the context of this document, “shallow” shall refer to a distance of no greater than about 1 micron from an outermost surface of a substrate material within which an isolation region is received.
A prior art method for forming a trench isolation region, such as a shallow trench isolation region, is described with reference to
FIGS. 1-2
.
FIG. 1
illustrates a semiconductor wafer fragment
10
at a preliminary step of the prior art processing method. Wafer fragment
10
comprises a substrate
12
, a pad oxide layer
14
over substrate
12
, and a silicon nitride layer
16
over pad oxide layer
14
. Substrate
12
can comprise, for example, a monocrystalline silicon wafer lightly doped with a p-type background dopant. Pad oxide layer
14
can comprise, for example, silicon dioxide.
Openings
22
extend through layers
14
and
16
, and into substrate
12
. Openings
22
can be formed by, for example, forming a patterned layer of photoresist over layers
14
and
16
to expose regions where openings
22
are to be formed and to cover other regions. The exposed regions can then be removed to form openings
22
, and subsequently the photoresist can be stripped from over layers
14
and
16
.
A first silicon dioxide layer
24
is formed within openings
22
to a thickness of, for example, about 100 Angstroms. First silicon dioxide layer
22
can be formed by, for example, heating substrate
12
in the presence of oxygen. A second silicon dioxide layer
26
is deposited within the openings by high density plasma deposition. In the context of this document, a high density plasma is a plasma having a density of greater than or equal to about 10
10
ions/cm
3
.
FIG. 1
is a view of wafer fragment
10
as opening
24
is partially filled with the deposited silicon dioxide, and
FIG. 2
is a view of the: wafer fragment after the openings have been completely filled. As shown in
FIG. 1
, the deposited silicon dioxide undesirably forms cups
28
at top portions of openings
22
. Specifically, cusps
28
are formed over corners of silicon nitride layer
16
corresponding to steps in elevation. The cusp formation (also referred to as “bread-loafing”) interferes with subsequent deposition of silicon dioxide layer
26
as shown in FIG.
2
. Specifically, the subsequently deposited silicon dioxide can fail to completely fill openings
22
, resulting in the formation of voids
29
, or “keyholes” within the deposited silicon dioxide layer
26
.
After providing second silicon dioxide layer
26
within openings
22
, the second silicon dioxide layer is planarized, preferably to a level slightly below an upper surface of nitride layer
16
, to form silicon dioxide plugs within openings. The silicon dioxide plugs define trench isolation regions within substrate
12
. Such trench isolation regions have voids
29
remaining within them. The voids define a space within the trench isolation regions having a different dielectric constant than the remainder of the trench isolation regions, and can undesirably allow current leakage through the trench isolation regions. Accordingly, it is desirable to develop methods of forming trench isolation regions wherein voids
29
are avoided.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses a method of forming a silicon dioxide layer. A high density plasma is formed proximate a substrate. The plasma comprises silicon dioxide precursors. Silicon dioxide is formed from the precursors and deposited over the substrate at a deposition rate. While the silicon dioxide is being deposited, it is etched with the plasma at an etch rate. A ratio of the deposition rate to the etch rate is at least about 4:1.
In another aspect, the invention encompasses a method of forming a silicon dioxide layer over a substrate wherein a temperature of the substrate is maintained at greater than or equal to about 500° C. during the deposition. More specifically, a high density plasma is formed proximate a substrate. Gases are flowed into the plasma, and at least some of the gases form silicon dioxide. The silicon dioxide is deposited over the substrate. While the silicon dioxide is being deposited, a temperature of the substrate is maintained at greater than or equal to about 500° C.
In another aspect, the invention encompasses a method of forming a silicon dioxide layer over a substrate wherein the substrate is not cooled during the deposition. More specifically, a high density plasma is formed proximate a substrate Gases are flowed into the plasma, and at least some of the gases form silicon dioxide. The silicon dioxide is deposited over the substrate. The substrate is not cooled with a coolant gas while depositing the silicon dioxide.
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Sandhu Gurtej S.
Sharan Sujit
Lee Jr. Granvill D
Wells St. John P.S.
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