Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2008-07-22
2008-07-22
Wilczewski, M. (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S692000
Reexamination Certificate
active
11181607
ABSTRACT:
Methods of forming a shallow trench isolation structures in semiconductor devices are disclosed. A disclosed method comprises forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate; forming a trench defining first and second active areas by etching the second oxide layer, the nitride layer, the first oxide layer, and the substrate in a predetermined area; forming a third oxide layer along an inside of the trench; forming a fourth oxide layer to fill up the trench; forming a sacrificial oxide layer on the fourth oxide layer; and removing the sacrificial oxide layer, the fourth oxide layer, the third oxide layer, the second oxide layer, and the nitride layer so as to form the shallow trench isolation. Thus, it is possible to minimize the damage of a narrow active area when forming an element isolation area through an STI process.
REFERENCES:
patent: 5077234 (1991-12-01), Scoopo et al.
patent: 5578518 (1996-11-01), Koike et al.
patent: 5691215 (1997-11-01), Dai et al.
patent: 5710076 (1998-01-01), Dai et al.
patent: 5834358 (1998-11-01), Pan et al.
patent: 5960297 (1999-09-01), Saki
patent: 6001708 (1999-12-01), Liu et al.
patent: 6022788 (2000-02-01), Gandy et al.
patent: 6037018 (2000-03-01), Jang et al.
patent: 6048775 (2000-04-01), Yao et al.
patent: 6121113 (2000-09-01), Takatsuka et al.
patent: 6177333 (2001-01-01), Rhodes
patent: 6225187 (2001-05-01), Huang et al.
patent: 6235608 (2001-05-01), Lin et al.
patent: 6261923 (2001-07-01), Kuo et al.
patent: 6319794 (2001-11-01), Akatsu et al.
patent: 6319796 (2001-11-01), Laparra et al.
patent: 6326309 (2001-12-01), Hatanaka et al.
patent: 6461932 (2002-10-01), Wang
patent: 6479361 (2002-11-01), Park
patent: 6528389 (2003-03-01), Allman et al.
patent: 6593208 (2003-07-01), Jin
patent: 6716718 (2004-04-01), Nagatani et al.
patent: 6818526 (2004-11-01), Mehrad et al.
patent: 7172914 (2007-02-01), Narayanan
patent: 2004/0077171 (2004-04-01), Chuang et al.
patent: 2004/0262641 (2004-12-01), Rhodes
Dongbu Electronics Co. Ltd.
Fortney Andrew D.
Wilczewski M.
LandOfFree
Methods of forming shallow trench isolation structures in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of forming shallow trench isolation structures in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming shallow trench isolation structures in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3957572