Single-crystal – oriented-crystal – and epitaxy growth processes; – Forming from vapor or gaseous state – With decomposition of a precursor
Reexamination Certificate
2000-04-12
2001-07-31
Kunemund, Robert (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Forming from vapor or gaseous state
With decomposition of a precursor
C117S094000, C117S095000, C117S935000, C438S524000, C438S694000, C216S017000, C216S039000
Reexamination Certificate
active
06267817
ABSTRACT:
TECHNICAL FIELD
The invention pertains to methods of forming semiconductive wafers, and to methods of alleviating slip generation within semiconductive wafers. The invention further pertains to methods of forming semiconductive ingots. Additionally, the invention pertains to semiconductive material ingots and to semiconductive material wafers.
BACKGROUND OF THE INVENTION
Semiconductive wafers are used as substrates for the formation of microprocessor, DRAM, logic, and memory circuits. Such semiconductive wafers can comprise, for example, silicon. Ideally, the semiconductive wafers will comprise a single crystal of semiconductive material. For instance, silicon wafers are generally taken from crystals grown by a Czochralski (CZ) method or a float zone (FZ) method. The CZ method comprises growing a crystalline ingot by dipping a seed crystal into a silicon melt and then slowly extracting the seed. Liquid from the silicon melt crystallizes on the seed as it is extracted. Preferably, oxygen and other impurities will be excluded as the silicon melt is crystallized. Otherwise, the impurities can become incorporated into the silicon crystal during growth and cause defects in the crystalline lattice. For instance, if oxygen is introduced during cooling of a silicon melt, an oxygen-induced stacking fault (OSF) will typically result. Such OSF can adversely affect circuit devices formed on the crystalline silicon if the fault moves to a surface of the silicon.
After formation of the semiconductive ingot, the ingot is cut into thin wafers. The wafers are then subjected to further processing to form integrated circuitry on them.
The processing to form integrated circuitry on the silicon wafer generally involves various heating and cooling steps. Such steps cause the wafer to radially expand and contract. The degree of expansion and contraction are frequently not equal at the center of the wafer relative to regions of the wafer more adjacent a radially outer periphery of the wafer. Such unequal or uneven expansion of regions of the wafer can result in sheer stress between vertically stacked planes of the crystalline lattice. As sheer stress can lead to adjacent planes in the crystalline lattice slipping or sliding relative to one another, the sheer stress can upset the monocrystalline lattice of the silicon wafer. Such slippage of the planes in the crystalline lattice is referred to herein as “slip generation”. Upsets in the lattice of the wafer can generate defects which adversely affect integrated circuits subsequently formed on the wafer.
A continuing trend in semiconductor wafer processing is to utilize larger and larger diameter wafers. Problems associated with lattice slipping are expected to become more pronounced as wafers become ever larger.
It would be desirable to develop methods for avoiding generation of lattice slippage in wafers, and to develop monocrystalline semiconductive material wafers and ingots treated to alleviate slippage within the crystalline lattices of the wafers and ingots.
SUMMARY OF THE INVENTION
The invention encompasses methods of treating semiconductive material wafers and ingots to alleviate slippage within monocrystalline lattices of the wafers and ingots. The invention further encompasses monocrystalline semiconductive material wafers and monocrystalline semiconductive ingots which are treated to alleviate slippage within a crystalline lattice of the wafers and ingots.
In one aspect, the invention includes a method of forming a semiconductive material wafer wherein an ingot of semiconductive material is formed, and wherein the ingot comprises an outer periphery. A wafer is formed from the ingot, and the wafer comprises the outer periphery. The outer periphery is doped with strength-enhancing dopant atoms.
In another aspect, the invention includes a method of forming a semiconductive material wafer wherein an ingot of semiconductive material is formed, and wherein the ingot comprises an outer periphery. A stacking fault and inducing material is implanted into the ingot to form stacking faults proximate the outer periphery of the ingot. The stacking fault inducing material can be an oxygen precipitant inducing material. A wafer is formed from the ingot, and the wafer comprises the stacking faults. If the stacking fault inducing material is an oxygen precipitant inducing material, the wafer can also comprise oxygen precipitants.
In another aspect, the invention includes a method of treating a semiconductive material wafer to alleviate slip generation wherein a portion of the wafer is masked to form a masked portion and an unmasked portion of the wafer. While masking the wafer, stacking faults are formed in the unmasked portion of the semiconductive material wafer.
In another aspect, the invention includes an ingot of semiconductive material having an outer periphery region which defines an outer boundary of the ingot, and having stacking faults formed within the outer periphery region.
In another aspect, the invention includes a wafer of semiconductive material having an outer periphery which comprises a peripheral edge at an outer boundary of the wafer. Strength-enhancing dopant atoms are provided within the outer periphery region such that a peak depth of the strength-enhancing dopant atoms is from about 0.3 microns to about 3 microns from the peripheral edge of the wafer.
REFERENCES:
patent: 4737468 (1988-04-01), Martin
patent: 5196358 (1993-03-01), Boos
patent: 2-114534 (1990-04-01), None
Noboro Akiyama, et al., Critical Radial Temperature Gradient Inducing Slip Dislocations in Silicon Epitaxy Using Dual Heating of the Two Surfaces of a Wafer,Japanese Journal of Applied Physics, vol. 15, Mo. 11, Nov. 1986, pp. 1619-1622.
Masaharu Watanabe, Technical Trends in Large Diameter Silicon Wafers: Part II,Solid State Technology, Apr. 1991, pp. 133-142.
J. S. Simon, et al., Influence of oxygen on the recombination strength of dislocations in silicon wafers,Materials Science and EngineeringB36 (1996), pp. 183-186.
Y. K. Kim, et al., Factors Affecting the Formation of Oxidation-Induced Stacking Fault Nuclei in Silicon Crystals Grown With Czochralski Method, Abstract No. 186, pp. 257-258.
A. Buczkowski, et al., Surface Recombination Velocity and Recombination Lifetime in Iron Contaminated Silicon, Department of Materials Science and Engineering, Abstract No. 291, pp. 478-479.
J. R. Patei, et al., Oxygen precipitation and stacking-fault formation in dislocation-free silicon,J. Appl. Phys.48 (12), Dec. 1977, pp. 5279-5288.
Cor L. Claeys, et al., The Influence of annealing ambient on the shrinkage kinetics of oxidation-induced stacking faults in silicon,Appl. Phys. Lett.35(10), Nov. 1979, pp. 797-798.
G. A. Rozganyi, et al. The Elimination of Stacking Faults by Preoxidation Gettering of Silicon Wafers, III. Defect Etch Pit Correlation wit p-n Junction Leakage,J. Electrochem. Soc.: Solid-State Science and Technology, Apr. 1976, pp. 570-576.
H.D. Chiou, et al., Effects of Oxygen and Nitrogen on Slip in Z Silicon Wafers,VLSI Science and Technology, 1984, pp. 58-65.
Defects and Radiation Effects in Semiconductors, 1980, Invited and contributed papers from the Eleventh International Conference on Defects and Radiation Effects in Semiconductors held in Oiso, Japan, Sep. 1980, pp. 400-407.
J.-P. Zollner, et al., Slip Generation during Rapid Thermal Processing,Phys. Stat. Sol.(a) 156 (1996), pp. 63-70.
Fredric Ericson, et al., Micromechanical fracture strength of silicon,J. Appl. Phys.68(11), Dec. 1990, pp. 5840-5844.
A. Misiuk, et al., Stress-induced oxygen precipitation in Cz-Si,Elsevier Materials Science and EngineeringB36 (1996), pp. 30-32.
K. N. Ritz, et al., Observation of slip dislocations in (100) silicon wafers after BF2ion implantation and rapid internal annealing,J. Appl. Phys.60 (2) Jul. 1986, pp. 800-802.
K. N. Ritz, et al., Observation of Slip Dislocation in (100) and (111) Silicon Wafers After Rapid Thermal Processing, Abstract No. 462, pp. 665-666.
Hirofumi Shimizu, et al., Thermal Warpage of Large Diameter Czochralski-Grown Silicon Wafers,J. Applied Phys.,
Kunemund Robert
Micro)n Technology, Inc.
Wells, St. John, Roberts Gregory & Matkin P.S.
LandOfFree
Methods of forming semiconductor wafers, methods of treating... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of forming semiconductor wafers, methods of treating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming semiconductor wafers, methods of treating... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2554996