Methods of forming semiconductor structures, and articles...

Details Methods of forming semiconductor structures, and articles... Methods of forming semiconductor structures, and articles...

2002-05-16

2004-08-03

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S070000

Reexamination Certificate

active

06770566

ABSTRACT:

BACKGROUND
This invention relates to the field of semiconductor technology and, more particularly, to the field of via-contacts.
Device densities and the number of components on semiconductor wafer surfaces have continued to increase in recent years. As a result, the surface areas available for wiring have decreased proportionately. One solution to this problem has been to design multilevel metallization structures, in which an insulating layer of dielectric material interposed between two metal layers is etched with via holes (also known as contact holes or plugs), which provide channels through the insulating layer for connecting the two metal layers. These channels may be filled with a conducting material (e.g., tungsten) to establish electrical contact between the metal layers.
Typical processing steps involved in the creation of a via are illustrated in
FIGS. 1-8
. The semiconductor structure
2
shown in
FIG. 1
is made by forming an insulating layer
4
(e.g., an oxide layer) over a fabricated cell and peripheral circuitry (not shown). The insulating layer
4
may be deposited by chemical vapor deposition (CVD) and then planarized using chemical mechanical polishing (CMP). A first metal structure
6
may then be deposited over insulating layer
4
. The first metal structure
6
may include a stacked metal structure, such as shown in
FIG. 1
, which includes a bottom layer
8
, a middle layer
10
, and a top layer
12
. Typically, a refractory metal such as TiW is employed for bottom layer
8
and top layer
12
. The refractory metal serves to prevent temperature-related hillock formation during subsequent processing, while enhancing electro- and stress-migration resistances and providing more reliable interconnections. Typically, a conducting metal such as aluminum or an aluminum alloy, which provides low resistivity interconnections, is employed as the middle layer
10
.
The metal structure
6
is then patterned using photolithography and etching, as illustrated in
FIGS. 2 and 3
. A photoresist
14
may be deposited on the top layer
12
of stacked metal structure
6
and then patterned as shown in
FIG. 2
to create mask openings
15
. The top layer
12
, the middle layer
10
, and the bottom layer
8
of stacked metal structure
6
are then successively etched through mask openings
15
to create openings
17
, as shown in FIG.
3
.
The photoresist
14
is stripped away and the resulting structure is cleaned to provide the semiconductor structure
2
shown in
FIG. 4. A
second insulating layer
16
(e.g., an oxide layer) is then deposited on the patterned stacked metal structure
6
(e.g., using CVD) in a manner analogous to that described above. As before, the structure can be planarized (e.g., using CMP) to provide the semiconductor structure
2
shown in FIG.
5
.
A via is formed in semiconductor structure
2
as illustrated in
FIGS. 6-8
. A second photoresist
18
may be deposited on second insulating layer
16
and patterned as described above to create a mask opening
19
, as shown in
FIG. 6. A
via
20
may be etched through mask opening
19
using photolithography and dry etching. Removal of the photoresist
18
provides the semiconductor structure
2
shown in
FIG. 7
, which may then be filled with a metal such as aluminum (e.g., by the aluminum flow method) or with a stacked metal structure
24
, as shown in
FIG. 8
, to complete the metallization process. The stacked metal structure
24
shown in
FIG. 8
includes a top layer
30
(e.g., Co—Ti), a middle layer
28
(aluminum), and a bottom layer
26
(e.g., TiW).
The conventional technique of via formation (i.e., the process for converting the structure depicted in
FIG. 6
to the structure depicted in
FIG. 7
) usually involves a dry etching process known as reactive ion etching (RIE), which exposes the middle layer
10
of aluminum to several potentially damaging influences, including radio frequency (RF) power damages and chemical attacks on the aluminum surface. As shown in
FIG. 7
, the top layer
12
of refractory metal is typically removed during reactive ion etching of the via, with the middle layer
10
of aluminum being damaged as a result. A gouge
22
in the aluminum is typically made, which serves to increase porosity and lower density, thus increasing the susceptibility of the aluminum to contamination from hydroxide ions (OH
−
) and hydroxide radicals (OH—) during wet chemical and water exposure.
The contaminated aluminum may have a detrimental effect on electrical contact with the second metal used to fill the via-contact. A porous interface or a void at the via-contact interface may result, which renders the via-contact readily susceptible to stress during reliability tests, and may lead to electrical degradation of the device, such as an increase in via-contact resistance. Furthermore, an open circuit may result from the disconnection of the two metal layers in the via-contact.
FIG. 9
shows an SEM photograph of a stress-induced void formed at the interface of a via-contact after burn-in test.
The present invention is directed to providing high quality via-contacts ao exhibiting good structural integrity.
SUMMARY
The scope of the present invention is defined solely by the appended claims, and is not affected to any degree by the statements within this summary.
In a first aspect, the present invention is a method of forming a semiconductor structure that includes etching a first metal layer at the bottom of a via in a first insulating layer to expose a second metal layer, wherein the first metal layer is on the second metal layer, and wherein the etching of the first metal layer is not reactive-ion etching.
In a second aspect, the present invention is a method of making a semiconductor device that includes making a semiconductor structure by the method described above, and forming a semiconductor device from the structure.
In a third aspect, the present invention is a method of making an electronic device that includes making a semiconductor device by the method described above, and forming an electronic device that includes the semiconductor device.


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