Semiconductor device manufacturing: process – Electron emitter manufacture
Reexamination Certificate
1999-07-23
2001-02-20
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Electron emitter manufacture
C438S022000, C438S030000
Reexamination Certificate
active
06190929
ABSTRACT:
TECHNICAL FIELD
The invention pertains to methods of forming semiconductor devices, such as, for example, cathode emitter tips for electron emission devices. In particular applications, the invention pertains to methods of forming a patterned mask by pressing a pliable masking material with a mold.
BACKGROUND OF THE INVENTION
Electron emission devices include display devices wherein electrons are emitted from cathode emitter tips toward phosphor molecules (the phosphor molecules can also be referred to herein as simply “phosphor”). An exemplary display device is a Field Emission Display (FED) device, such as the prior art FED device
10
described with reference to FIG.
1
.
Device
10
comprises a baseplate assembly
12
and a faceplate assembly
14
. Baseplate assembly
12
includes a substrate
16
. Substrate
16
is preferably formed of an insulative glass material, and can be referred to as a baseplate. Column interconnects
18
are patterned over substrate
16
. Column interconnects
18
comprise a conductive material, such as, for example, a metal. In preferred applications, column interconnects comprise an assembly of three sub-layers, with the sub-layers being an aluminum layer elevationally between a pair of chromium layers.
A buffer layer
19
is formed over column interconnects
18
, and a resistor layer
20
is formed over buffer layer
19
. Buffer layer
19
comprises amorphous or microcrystalline silicon, and resistor layer
20
comprises conductively-doped amorphous silicon (preferably, boron-doped amorphous silicon).
Electron emission tips
22
are formed over substrate
16
at sites from which electrons are to be emitted, and can be constructed from conductively doped silicon (the silicon can be in, for example, either an amorphous or polycrystalline form). Emission tips
22
can have a number of pointed geometries, including, for example, pyramids and cones.
An extraction grid
24
(also referred to as a gate) is formed proximate emitter tips
22
, and separated from substrate
16
with a dielectric layer
26
. Extraction grid
24
comprises a conductive material, such as, for example, conductively doped polysilicon. Extraction grid
24
is patterned to have openings
28
extending therethrough to expose electron emission tips
22
. Dielectric layer
26
electrically insulates extraction grid
24
from electron emission tips
22
, and the associated column interconnects
18
.
Faceplate assembly
14
of FED device
10
is provided in a spaced relation relative to baseplate assembly
12
, and is held in such spaced relation by insulative spacers
38
.
Faceplate assembly
14
comprises a transparent substrate
36
, and a transparent anode
34
formed proximate substrate
36
. Substrate
36
can be referred to as a faceplate. Anode
34
can comprise, for example, indium tin oxide, and substrate
36
can comprise, for example, glass.
Faceplate assembly
14
comprises phosphor
32
supported by substrate
36
and defining pixels. Phosphor
32
comprises a luminescent material that generates visible light upon being excited by electrons emitted from electron emission tips
22
. Phosphor
32
can comprise, for example, red/green/blue phosphor triads.
A voltage source
30
is provided to generate an operating voltage differential between electron emission tips
22
, grid structure
24
, and anode
34
. One or more of emitter tips
22
can then be electrically stimulated to cause electrons
40
to be emitted toward phosphor
32
. The impact of electrons
40
with phosphor
32
causes luminescence of phosphor
32
. A person looking through transparent substrate
36
can see such luminescence. Accordingly, electron emission from emitter tips
22
is converted to an image visible through faceplate assembly
16
.
Clarity, or resolution, of a field emission display is a function of a number of factors, including emitter tip uniformity and sharpness. Accordingly, numerous methods have been proposed for fabrication of very sharp emitter tips (i.e., emitter tips having tip radii of 100 nanometers or less), uniformly spaced across an array. Fabrication of very sharp and appropriately spaced tips has, however, proved difficult. In light of these difficulties, it would be desirable to develop alternative methods of forming emitter tips.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses a method of forming a semiconductor device. A masking material is formed over a semiconductor substrate. A mold is provided, and the mold has a first pattern defined by projections and valleys between the projection. The masking material is pressed between the mold and the substrate to form a second pattern in the masking material. The second pattern is substantially complementary to the first pattern. The mold is removed from the masking material, and subsequently the masking material is utilized as a mask during etching of the semiconductor substrate.
In another aspect, the invention encompasses a method of forming a field emission display. A first material layer is formed over a conductive substrate, and a masking material is formed over the first material layer. A mold is provided over the mask material, and the mask material is pressed between the mold and the first material layer to pattern the masking material. The pattern is transferred from the masking material to the first material layer. The patterned first material layer is then used as a second mask, and the conductive substrate is etched to form a plurality of conically shaped emitters. A display screen is formed in a spaced relation to such emitters.
REFERENCES:
patent: 5509840 (1996-04-01), Huang et al.
Stephen Y. Chou et al.; “Sub-10 nm imprint lithography and applications”; J. Vac. Sci. Technol. B, vol. 15, No. 6, Nov./Dec. 1997; pp. 2897-2904.
Heidari, B. et al., “Large Scale Nanolithography Using Nanoimprint Lithography”, J. Vac. Sci. Technol. B 17(6), Nov./Dec. 1999, pp. 2961-2964.
Wang, J. et al., “Fabrication of a New Broadband Waveguide Polarizer with a Double-Layer 190 nm Period Metal-Gratings Using Nanoimprint Lithography”, J. Vac. Sci. Technol. B 17(6), Nov./Dec. 1999, pp. 2957-2960.
Ruchhoeft, P. et al., “Patterning Curved Surfaces: Template Generation by Ion Beam Proximity Lithography and Relief Transfer by Step and Flash Imprint Lithography”, J. Vac. Sci. Technol. B 17(6), Nov./Dec. 1999, pp. 2965-2969.
Haisma, J. et al., “Mold-Assisted Nanolithography: A Process for Reliable Pattern Replication” J. Vac. Sci. Technol. B 14(6), Nov./Dec. 1996, pp. 4124-4128.
Hofmann James
Wang Dapeng
Collins D. M.
Micro)n Technology, Inc.
Picardat Kevin M.
Wells, St. John, Roberts Gregory & Matkin P.S.
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