Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2001-10-16
2003-05-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S238000
Reexamination Certificate
active
06566222
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor manufacturing. More particularly, the present invention provides methods of forming capacitor structures including recessed hemispherical grain silicon.
BACKGROUND OF THE INVENTION
In the fabrication of integrated circuits, various conductive layers are used. For example, during the formation of semiconductor devices, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), ferroelectric (FE) memories, etc., conductive materials are used in the formation of storage cell capacitors and also may be used in interconnection structures, e.g., conductive layers of contact holes, vias, etc.
As memory devices become more dense, it is necessary to decrease the size of circuit components forming such devices. One way to retain storage capacity of storage cell capacitors of the memory devices and at the same time decrease the memory device size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. Therefore, high dielectric constant materials are used in such applications interposed between two electrodes. One or more layers of various conductive materials may be used as the electrode material.
Further, to the increase the capacitance for a storage cell capacitor of a memory device without increasing the occupation area of the storage cell capacitor, various techniques have been used to increase the surface area of the lower electrode of the capacitor. For example, hemispherical grains (HSG) have been used to enhance such surface area of the lower electrode of a capacitor of a memory device.
However, in many cases, the use of HSG to enhance surface area of an electrode can be problematic. The manufacturing of container capacitors, such as is described in U.S. Pat. No. 5,270,241 (Dennison et al.) involves a simulation process whereby the continuous conductive material lining the containers and extending between them on the upper surface of the structure is partially removed to separate the conductive material within a container from the conductive material in the other containers. Simulation may be accomplished using a chemical mechanical polishing (CMP) step which removes only the uppermost horizontal expanses of the continuous conductive layer.
Although CMP is effective at separating the containers, it leaves a structure in which the hemispherical grain silicon precursor layer (i.e., the layer from which the hemispherical grain silicon is formed) and the underlying doped silicon layer both extend to the upper edge of the capacitor plates. As a result, after conversion of the hemispherical grain silicon precursor layer to a layer of hemispherical grain silicon by, e.g., seeding and annealing or any other suitable technique, the hemispherical grain silicon layer typically extends above the outer layer of doped silicon along the edges of the capacitor plates.
Grains or particles from the edge of the hemispherical grain silicon layer are, however, susceptible to separation from the hemispherical grain silicon layer. Once separated or broken off, the loose particles can fall between adjacent capacitors because they extend above the outer layers of the containers, resulting in electrical shorts between the adjacent capacitors. Such defects adversely affect the output of the manufacturing processes used to form the capacitors. Although typically associated with cup-shaped capacitors, these problems may also be experienced in connection with other capacitor structures, e.g., trench, tub, etc.
SUMMARY OF THE INVENTION
The present invention provides methods of manufacturing capacitor structures with edge zones that are substantially free of hemispherical grain silicon along the upper edges of the capacitor structures. The resulting recessed hemispherical grain silicon layers reduce or prevent separation of particles from the hemispherical grain silicon layer during subsequent manufacturing processes, thereby reducing defects and increasing throughput.
Among the methods of the present invention are methods of forming the capacitor structures in which the silicon layer used to form the hemispherical grain silicon is selectively doped. That selective doping provides an edge zone that does not convert to hemispherical grain silicon during manufacturing.
In one aspect, the present invention provides a method of forming a capacitor structure by: providing a cavity in a substrate, the cavity including a sidewall structure, an opening in the upper surface of the substrate, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer is electrically conductive; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon precursor; selectively doping the hemispherical grain silicon precursor in the second layer within an edge zone on the sidewall structure, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and converting the undoped hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein the edge zone is substantially free of the hemispherical grain silicon.
In another aspect, the present invention provides a method of forming a capacitor structure by: providing a cavity in a substrate, the cavity including a sidewall structure, an opening in the upper surface of the substrate, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer is electrically conductive; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon precursor; selectively doping the hemispherical grain silicon precursor in the second layer within an edge zone on the sidewall structure, the edge zone extending from the opening of the cavity towards the bottom of the cavity, wherein selectively doping includes implanting the hemispherical grain silicon precursor in the second layer with a dopant; and converting the undoped hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein the edge zone is substantially free of the hemispherical grain silicon.
In another aspect, the present invention provides a method of forming a capacitor structure by: providing a cavity in a substrate, the cavity including a sidewall structure, an opening in the upper surface of the substrate, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer is electrically conductive; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon precursor; selectively doping the hemispherical grain silicon precursor in the second layer within an edge zone on the sidewall structure, the edge zone extending from the opening of the cavity towards the bottom of the cavity, wherein selectively doping includes implanting the hemispherical grain silicon precursor in the second layer with a dopant, the dopant being directed at an implantation angle relative to the sidewall structure of the cavity; and converting the undoped hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein the edge zone is substantially free of the hemispherical grain silicon.
In another aspect, the present invention provides a method of forming a capacitor structure by: providing a cavity in a substrate, the cavity including a sidewall structure, an opening in the upper surface of the substrate, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer is electrically conductive; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon precursor; selectively doping the hemispherical grain silicon precursor in the second layer wi
Micro)n Technology, Inc.
Mueting Raasch & Gebhardt, P.A.
Nelms David
Vu David
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