Methods of forming planarized multilevel metallization in an...

Details Methods of forming planarized multilevel metallization in an... Methods of forming planarized multilevel metallization in an...

2008-01-01

2008-01-01

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

C438S622000, C257SE21170, C257SE21229, C257SE21029

Reexamination Certificate

active

07314813

ABSTRACT:
A method is provided for forming a semiconductor device that reduces metal-stress-induced photo misalignment by incorporating a multi-layered anti-reflective coating over a metal layer. The method includes providing a substrate with a conductive layer formed over the substrate, depositing a multi-layered anti-reflective coating (including alternating layers of titanium and titanium nitride), defining a plurality of conductive lines in connection with a first etching step, depositing a dielectric layer, and defining at least one via in connection with a second etching step.

REFERENCES:
patent: 6057603 (2000-05-01), Dawson
patent: 6124640 (2000-09-01), Sahota et al.
patent: 6339027 (2002-01-01), Chok
patent: 6992393 (2006-01-01), Huang et al.

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