Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2005-09-27
2005-09-27
Huynh, Andy (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S250000, C438S251000, C438S253000, C438S393000, C438S394000
Reexamination Certificate
active
06949442
ABSTRACT:
A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.
REFERENCES:
patent: 5397729 (1995-03-01), Kayanuma et al.
patent: 5547890 (1996-08-01), Tseng
patent: 5731220 (1998-03-01), Tsu et al.
patent: 5741721 (1998-04-01), Stevens
patent: 5851873 (1998-12-01), Murai et al.
patent: 5994182 (1999-11-01), González et al.
patent: 6066892 (2000-05-01), Ding et al.
patent: 6087213 (2000-07-01), Murai et al.
patent: 6159790 (2000-12-01), Gonzalez et al.
patent: 6197650 (2001-03-01), Wu
patent: 6211545 (2001-04-01), Gonzalez et al.
patent: 6221730 (2001-04-01), Honma
patent: 6235579 (2001-05-01), Lou
patent: 6238964 (2001-05-01), Cho
patent: 6294420 (2001-09-01), Tsu et al.
patent: 6313003 (2001-11-01), Chen
patent: 6329234 (2001-12-01), Ma et al.
patent: 6372574 (2002-04-01), Lane et al.
patent: 6451664 (2002-09-01), Barth et al.
patent: 6466427 (2002-10-01), Chen
patent: 6509267 (2003-01-01), Woo et al.
patent: 6576525 (2003-06-01), Stamper
patent: 6579785 (2003-06-01), Toyoda et al.
patent: 6593185 (2003-07-01), Tsai et al.
patent: 6613641 (2003-09-01), Volant et al.
patent: 6649464 (2003-11-01), Lee
patent: 6670237 (2003-12-01), Loh et al.
patent: 6716741 (2004-04-01), Chang et al.
patent: 6794262 (2004-09-01), Ning et al.
patent: 2002/0027286 (2002-03-01), Sundararajan et al.
patent: 2002/0096775 (2002-07-01), Ning
patent: 2003/0228749 (2003-12-01), Sinha et al.
Kikkawa, T., “A photosensitive low-k interlayer-dielectric film for ULSIs,” IEEE, 2001, pp. 348-351.
Segawa, Y., et al., “Manufacturing-ready Selectivity of CoWP Capping on Damascene Copper Interconnects,” Conference Proceedings ULSI XVII, 2002, Materials Research Society, pp. 567-572.
Kikkawa, Takamaro, “Current and Furture Low-k Dielectrics for Cu Interconnects,” IEEE (2000) Research Center for Nanodevices and Systems, Hiroshima University, Higashi-Hiroshima, Japan.
Liu, et al., “Single Mask Metal-Insulator-Metal (MIM) Capacitor with Copper Damascene Metalization for Sub-0.18 μm Mixed Mode Signal and System-on-a-Chip (SoC) Applications,” Proceedings IITC 2000, IEEE, 2000, pp. 111-113.
Lopatin, et al., “Thin Electroless Barrier for Cooper Films,” SPIE Conference on Multilevel Interconnect Technology II, Sep. 1998, vol. 3508, pp. 65-77.
Mahnkopf, et al., System on a Chip′ Technology Platform for 0.18 μm Digital, Mixed Signal & eDRAM Applications, IEDM, 1999, pp. 849-852.
Barth Hans-Joachim
Felsner Petra
Friese Gerald R.
Kaltalioglu Erdem
Huynh Andy
Infineon - Technologies AG
Slater & Matsil L.L.P.
LandOfFree
Methods of forming MIM capacitors does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of forming MIM capacitors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming MIM capacitors will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3412816