Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2007-05-15
2007-05-15
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S404000, C438S424000
Reexamination Certificate
active
11059770
ABSTRACT:
The invention includes methods of forming integrated circuitry. In one implementation, a method of forming an integrated circuit includes forming a plurality of isolation trenches within semiconductive silicon-comprising material. The isolation trenches comprise sidewalls comprising exposed semiconductive silicon-comprising material. An epitaxial silicon-comprising layer is grown from the exposed semiconductive silicon-comprising material sidewalls within the isolation trenches. Electrically insulative trench isolation material is formed within the isolation trenches over the epitaxially-grown silicon-comprising layer. Other aspects and implementations are contemplated.
REFERENCES:
patent: 3990927 (1976-11-01), Montier
patent: 4474975 (1984-10-01), Clemons et al.
patent: 5105253 (1992-04-01), Pollock
patent: 5156881 (1992-10-01), Okano et al.
patent: 5182221 (1993-01-01), Sato
patent: 5387539 (1995-02-01), Yang et al.
patent: 5410176 (1995-04-01), Liou et al.
patent: 5470798 (1995-11-01), Ouellet
patent: 5604149 (1997-02-01), Paoli et al.
patent: 5616513 (1997-04-01), Shepard
patent: 5702977 (1997-12-01), Jang et al.
patent: 5719085 (1998-02-01), Moon et al.
patent: 5741740 (1998-04-01), Jang et al.
patent: 5770469 (1998-06-01), Uram et al.
patent: 5776557 (1998-07-01), Okano et al.
patent: 5786039 (1998-07-01), Brouquet
patent: 5786263 (1998-07-01), Perera
patent: 5801083 (1998-09-01), Yu et al.
patent: 5863827 (1999-01-01), Joyner
patent: 5883006 (1999-03-01), Iba
patent: 5888880 (1999-03-01), Gardner et al.
patent: 5895253 (1999-04-01), Akram
patent: 5895255 (1999-04-01), Tsuchiaki
patent: 5904540 (1999-05-01), Sheng et al.
patent: 5923073 (1999-07-01), Aoki et al.
patent: 5930645 (1999-07-01), Lyons et al.
patent: 5930646 (1999-07-01), Gerung et al.
patent: 5943585 (1999-08-01), May et al.
patent: 5950094 (1999-09-01), Lin et al.
patent: 5960299 (1999-09-01), Yew et al.
patent: 5972773 (1999-10-01), Liu et al.
patent: 5976949 (1999-11-01), Chen
patent: 5981354 (1999-11-01), Spikes et al.
patent: 5989978 (1999-11-01), Peidous
patent: 5998280 (1999-12-01), Bergemont et al.
patent: 6013583 (2000-01-01), Ajmera et al.
patent: 6030881 (2000-02-01), Papasouliotis et al.
patent: 6033961 (2000-03-01), Xu et al.
patent: 6051477 (2000-04-01), Nam
patent: 6090675 (2000-07-01), Lee et al.
patent: 6156674 (2000-12-01), Li et al.
patent: 6171962 (2001-01-01), Karlsson et al.
patent: 6187651 (2001-02-01), Oh
patent: 6190979 (2001-02-01), Radens et al.
patent: 6191002 (2001-02-01), Koyanagi
patent: 6300219 (2001-10-01), Doan et al.
patent: 6326282 (2001-12-01), Park et al.
patent: 6329266 (2001-12-01), Hwang et al.
patent: 6355966 (2002-03-01), Trivedi
patent: 6448150 (2002-09-01), Tsai et al.
patent: 6455394 (2002-09-01), Iyer et al.
patent: 6534395 (2003-03-01), Werkhoven et al.
patent: 6583028 (2003-06-01), Doan et al.
patent: 6583060 (2003-06-01), Trivedi
patent: 6617251 (2003-09-01), Kamath et al.
patent: 6719012 (2004-04-01), Doan et al.
patent: 2001/0006255 (2001-07-01), Kwon et al.
patent: 2001/0006839 (2001-07-01), Yeo
patent: 2001/0041250 (2001-11-01), Haukka et al.
patent: 2001/0046753 (2001-11-01), Gonzales et al.
patent: 2002/0000195 (2002-01-01), Kao et al.
patent: 2002/0004284 (2002-01-01), Chen
patent: 2002/0018849 (2002-02-01), George et al.
patent: 2003/0032281 (2003-02-01), Werkhoven et al.
patent: 2003/0129826 (2003-07-01), Werkhoven et al.
patent: 2004/0032006 (2004-02-01), Yun et al.
patent: 2004/0082181 (2004-04-01), Doan et al.
patent: 2004/0209484 (2004-10-01), Hill et al.
patent: 2004/0266153 (2004-12-01), Yongjun
patent: 2005/0009368 (2005-01-01), Vaarstra
patent: 2005/0054213 (2005-03-01), Derderian et al.
patent: 2005/0079730 (2005-04-01), Beintner et al.
patent: 2005/0112282 (2005-05-01), Gordon et al.
patent: 2005/0124171 (2005-06-01), Vaarstra
patent: 2005/0142799 (2005-06-01), Seo
patent: 0817251 (1998-01-01), None
patent: 02277253 (1990-11-01), None
patent: 05-315441 (1993-11-01), None
patent: 06-334031 (1994-12-01), None
patent: 146224 (1996-01-01), None
patent: 02/27063 (2002-04-01), None
Beekmann et al.,Sub-micron Gap Fill and in-Situ Planarisation Using Flowfill™ Technology, Electrotech 1-7 ULSI Conference, Portland, OR (Oct. 1995).
Curtis, et al.,APCVD TEOS: O3Advanced Trench Isolation Applications, Semiconductor Fabtech, 9thEd., pp. 241-247 (pre-Jul. 2003).
Disclosed Anonymous 32246,Substrate Contact With Closed Bottom Trenches, Research Disclosure, 1 page (Feb. 1991).
Gasser et al.,Quasi-monolayer deposition of silicon dioxide, 250 Thin Solid Films, pp. 213-218 (1994).
George et al.,Atomic layer controlled deposition of SiO2and Al2O2using ABAB . . . binary reaction sequence Chemistry, 82/83 Applied Surface Science, pp. 460-467 (1994).
Hasumann et al.,Catalytic vapor deposition of highly conformal silica nanolaminates, Department of Chemistry and Chemical Biology, Harvard University, pp. 1-13 (May 14, 2002).
Chen et al.,Excimer Laser-Induced Ti Silicidation to Eliminate the Fine-Line Effect for Integrated Circuity Device Fabrication, 149 Journal of Electrochemical Society, No. 11, pp. G609-G612 (2002).
Nishiyama et al.,Agglomeration Resistant Self-Aligned Silicide Process Using N2Implantation into TiSi2, 36 Jpn. J. Appl. Phys., Part 1, No. 6A, pp. 3639-3643 (Jun. 1997).
Wolf,Chapter 13: Polycides and Salicides of TiSix, CoSi2, and NiSi, Silicon Processing for the VLSI Era, vol. IV, pp. 603-604 (pre-2003).
Hausmann et al.,Rapid Vapor Deposition of Highly Conformal Silica Nanolaminates, 298 Science, pp. 402-406 (Oct. 11, 2002).
Horie et al.,Kinetics and Mechanism of the Reactions of O(3P)with SiH4, CH3SiH3, (CH3)2SiH2, and(CH3)2SiH, 95 J. Phys. Chem., pp. 4393-4400 (1991).
Joshi et al.,Plasma Deposited Organosilicon Hydride Network Polymers as Versatile Resists for Entirely Dry Mid-Deep UV Photolithography, 1925 SPIE, pp. 709-720 (1993).
PCT/US2004/021156; Filed Jun. 30, 2004 Search Report.
Kiermasz et al.,Planarisation for Sub-Micron Devices Utilising a New Chemistry, 1-2 Electrotech, DUMIC Conference, California (Feb. 1995).
Klaus et al.,Atomic Layer Deposition of SiO2Using Catalyzed and Uncatalyzed Self-Limiting Surface Reactions, 6 Surface Review and Letters, Nos. 3 & 4, pp. 435-448 (1999).
Kojima et al.,Planarization Process Using a Multi-Coating of Spin-on-Glass, V-MIC Conference, California, 2 pages (1995).
Matsuura et al.,A Highly Reliable Self-planarizing Low-k Intermetal Dielectric for Sub-quarter Micron Interconnects, IEEE, pp. 785-788 (1997).
Matsuura et al.,Novel Self-planarizing CVD Oxide for Interlayer Dielectric Applications, IEEE, pp. 117-120 (1994).
McClatchie et al.,Low Dielectric Constant Flowfill™ Technology for IMD Applications, 7 pps. (pre-Aug. 1999).
Miller et al.,Self-limiting chemical vapor deposition of an ultra-thin silicon oxide film using bi-(tert-butoxy)silanol, 397 Thin Solid Films, pp. 78-82 (2001).
Morishita et al.,Atomic-layer chemical-vapor-deposition of silicon-nitride, 112 Applied Surface Science, pp. 189-204 (1997).
Shareef et al.,Subatmospheric chemical vapor deposition ozone/TEOS process for SiO2trench filling, J. Vac. Sci. Technol. B 13(4), pp. 1888-1995 (Jul./Aug. 1995).
U.S. Appl. No. 10/806,923, filed Mar. 22, 2004, Li et al.
U.S. Appl. No. 10/931,524, filed Aug. 31, 2004, Sandhu.
Withnall et al.,Matrix Reactions of Methylsilanes and Oxygen Atoms, 92 J. Phys. Chem., pp. 594-602, 1988.
Yokoyama et al.,Atomic layer controlled deposition of silicon nitride and in situ growth observation by infrared reflection absorption spectroscopy, 112 Applied Surface Science, pp. 75-81 (1997).
Dang Phuc T.
Wells St. John P.S.
LandOfFree
Methods of forming integrated circuitry does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of forming integrated circuitry, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming integrated circuitry will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3798596