Methods of forming HSG capacitors from nonuniformly doped...

Details Methods of forming HSG capacitors from nonuniformly doped... Methods of forming HSG capacitors from nonuniformly doped...

2000-01-19

2002-05-07

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Capacitor protection

C361S115000

Reexamination Certificate

active

06385020

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to methods of forming integrated circuit devices, and more particularly to methods of forming integrated circuit capacitors.
BACKGROUND OF THE INVENTION
The demand for higher capacity semiconductor memory devices has resulted in improved techniques to form memory devices and structures therein at higher levels of integration. However, because higher levels of integration typically require memory devices having smaller unit cell size, the area occupied by a cell capacitor in a memory device, such as a DRAM device, may have to be reduced significantly. As will be understood by those skilled in the art, this reduction in cell capacitor area can degrade memory cell performance if concomitant reductions in cell capacitance also occur.
Conventional methods of increasing cell capacitance include the use of thinner dielectric layers, high dielectric strength material and three-dimensional capacitor electrode structures. Conventional methods of increasing cell capacitor area also include forming cell capacitor electrodes (e.g., storage electrodes) with hemispherical grain (HSG) silicon surface layers. For example, a conventional method of forming HSG silicon surface layers on cell capacitor electrodes is disclosed in U.S. Pat. No. 5,407,534 to Thakur. The basic structure of an HSG capacitor is also disclosed in U.S. Pat. No. 5,597,756 to Fazan et al. However, while capacitors having HSG surface layers therein (hereinafter “HSG capacitors”) have manifested enhanced capacitance in high density integrated circuits, HSG capacitors may lack stability and may incur performance degradation over the lifetime of an integrated circuit memory device when formed using conventional methods.
Such conventional methods of forming HSG capacitor electrodes may include the use of amorphous silicon and silane gas as a seed gas, with silicon atom migration taking place in a vacuum atmosphere. Alternatively, impurity doped amorphous silicon layers may be used to form HSGs without requiring seeding. As will be understood by those skilled in the art, the silicon atom migration rate during HSG formation may vary depending on the seeding time, the seed gas flow rate and temperature and pressure. The level of impurity doping concentration in amorphous silicon layers may also determine the size, quantity and rate at which HSGs form from amorphous silicon layers.
Referring now to
FIGS. 1-3
, conventional methods of forming HSG capacitors will be described. As illustrated by
FIG. 1
, a conventional method of forming an HSG capacitor may include the steps of forming a plurality of conductive plugs
20
on a substrate containing an electrically insulating layer
10
thereon. A plurality of amorphous silicon patterns
30
may also be formed on respective conductive plugs
20
, as illustrated. Conventional HSG formation techniques are used to increase the surface area of the amorphous silicon patterns
30
by forming HSGs thereon. A dielectric layer
40
and upper capacitor electrode
50
are then formed to complete the integrated circuit capacitor structure. As illustrated by
FIG. 2
, the surface area of each lower capacitor electrode may be increased by forming U-shaped amorphous silicon patterns
32
as three-dimensional electrodes. However, while such U-shaped amorphous silicon patterns
32
may have increased surface area for a given lateral “footprint” or cell size, the formation of HSGs on the outer sidewalls of the U-shaped patterns
32
may increase the likelihood of reliability failures if HSGs on adjacent patterns
32
become electrically connected to each other by silicon “bridges” that may form during the HSG formation steps. In addition, the formation of HSGs typically causes migration of silicon atoms within the U-shaped patterns
32
and such migration, if excessive, may result in an undesirable and nonuniform thinning of the U-shaped patterns
32
. Such thinning may make the U-shaped patterns
32
more susceptible to fracture and breakage during subsequent process steps. To address these limitations associated with the capacitors of
FIG. 2
, steps may taken to mask the outer sidewalls of each U-shaped pattern during HSG formation. Thus, as illustrated by
FIG. 3
, conventional methods may include the steps of forming HSGs only on the enclosed upper surfaces of the U-shaped patterns
34
.
Notwithstanding these conventional techniques, improved methods of forming HSG capacitors are still needed to address limitations associated with conventional methods.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of forming integrated circuit capacitors and capacitors formed thereby.
It is another object of the present invention to provide methods of forming integrated circuit capacitors having high capacitance values and capacitors formed thereby.
It is still another object of the present invention to provide methods of forming integrated circuit capacitors having uniform capacitance characteristics across an integrated circuit substrate and capacitors formed thereby.
It is a further object of the present invention to provide methods of forming integrated circuit capacitors having highly uniform capacitance characteristics when reversed and forward biased and capacitors formed thereby.
It is still another object of the present invention to provide methods of forming integrated circuits having capacitors therein with improved long-term reliability.
These and other objects, advantages and features of the present invention are provided by methods of forming integrated circuit capacitors that include the steps of forming a first capacitor electrode (e.g., lower electrode) containing hemispherical grains (HSGs) of silicon from an amorphous silicon layer having a nonuniform doping profile therein. According to a preferred aspect of the present invention, the nonuniform doping profile in the amorphous silicon layer includes a high-to-low doping gradient in a direction extending towards an upper surface thereof. Steps are then performed to form a dielectric layer on the first capacitor electrode and form a second capacitor electrode on the dielectric layer, opposite the first capacitor electrode.
The high-to-low doping gradient in the amorphous silicon layer is preferably achieved by forming the amorphous silicon layer as a composite of a plurality of amorphous silicon layers having different concentrations of dopants therein which may be added using in-situ doping techniques. For example, the first capacitor electrode may be formed by depositing a lower amorphous silicon layer having a relatively high doping concentration therein on a substrate and then depositing an upper amorphous silicon layer having a relatively low doping concentration therein on the lower amorphous silicon layer. Because of the lower doping concentration in the upper amorphous silicon layer (relative to the lower amorphous silicon layer), steps to convert the upper amorphous silicon layer into an HSG layer will result in the formation of an HSG layer with relatively large silicon grains and potentially uneven thickness. However, because silicon atom migration is suppressed in the relatively highly doped amorphous silicon layer, the conversion steps may not contribute significantly to the migration of silicon atoms from the lower more highly doped amorphous silicon layer. Thus, the lower amorphous silicon layer will remain essentially intact during the conversion steps with only relatively small HSGs being formed thereon. More uniform capacitance can therefore be achieved (across a substrate and from wafer-to-wafer) by increasing the uniformity of the thicknesses of the resulting HSG lower capacitor electrodes. Increased reliability can also be achieved by reducing the likelihood of “bridging” between adjacent lower capacitor electrodes on a highly integrated substrate (i.e., between the HSGs on adjacent capacitors). This increased reliability is achieved by forming no HSGs or only relatively small HSGs on those portions of adjacent lower

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