Methods of forming field emitter display (FED) assemblies

Details Methods of forming field emitter display (FED) assemblies Methods of forming field emitter display (FED) assemblies

2002-04-01

2004-09-14

Williams, Joseph (Department: 2879)

Electric lamp or space discharge component or device manufacturi

Process

With assembly or disassembly

C445S050000

Reexamination Certificate

active

06790114

ABSTRACT:

TECHNICAL FIELD
This invention relates to field emitter display (FED) assemblies, and to methods of forming field emitter display (FED) assemblies.
BACKGROUND OF THE INVENTION
Flat-panel displays are widely used to visually display information where the physical thickness and bulk of a conventional cathode ray tube is unacceptable or impractical. Portable electronic devices and systems have benefitted from the use of flat-panel displays, which require less space and result in a lighter, more compact display system than provided by conventional cathode ray tube technology.
The invention described below is concerned primarily with field emission flat-panel displays or FEDs. In a field emission flat-panel display, an electron emitting cathode plate is separated from a display face or face plate at a relatively small, uniform distance. The intervening space between these elements is evacuated. Field emission displays have the outward appearance of a CRT except that they are very thin. While being simple, they are also capable of very high resolutions. In some cases they can be assembled by use of technology already used in integrated circuit production.
Field emission flat-panel displays utilize field emission devices, in groups or individually, to emit electrons that energize a cathodoluminescent material deposited on a surface of a viewing screen or display face plate. The emitted electrons originate from an emitter or cathode electrode at a region of geometric discontinuity having a sharp edge or tip. Electron emission is induced by application of potentials of appropriate polarization and magnitude to the various electrodes of the field emission device display, which are typically arranged in a two-dimensional matrix array.
Field emission display devices differ operationally from cathode ray tube displays in that information is not impressed onto the viewing screen by means of a scanned electron beam, but rather by selectively controlling the electron emission from individual emitters or select groups of emitters in an array. This is commonly known as “pixel addressing.” Various displays are described in U.S. Pat. Nos. 5,655,940, 5,661,531, 5,754,149, 5,563,470, and 5,598,057 the disclosures of which are incorporated by reference herein.
FIG. 1
illustrates a cross-sectional view of an exemplary field emission display (FED) device
10
. Device
10
comprises a face plate
12
, a base plate
14
, and spacers
16
extending between base plate
14
and face plate
12
to maintain face plate
12
in spaced relation relative to base plate
14
. Face plate
12
, base plate
14
and spacers
16
can comprise, for example, glass. Phosphor regions
18
,
20
, and
22
are associated with face plate
12
, and separated from face plate
12
by a transparent conductive layer
24
. Transparent conductive layer
24
can comprise, for example, indium tin oxide or tin oxide. Phosphor regions
18
,
20
, and
22
comprise phosphor-containing masses. Each of phosphor regions
18
,
20
, and
22
can comprise a different color phosphor. Typically, the phosphor regions comprise either red, green or blue phosphor. A black matrix material
26
is provided to separate phosphor regions
18
,
20
, and
22
from one another. The three phosphor colors (red, green, and blue) can be utilized to generate a wide array of screen colors by simultaneously stimulating one or more of the red, green and blue regions.
Base plate
14
has emitter regions
28
,
30
and
32
associated therewith. The emitter regions comprise emitters or field emitter tips
34
which are located within apertures
36
(only some of which are labeled) formed through a conductive gate layer or row line
38
and a lower insulating layer
40
. Emitters
34
are typically about 1 micron high, and are separated from base plate
14
by a conductive layer
42
. Emitters
34
and apertures
36
are connected with circuitry (not shown) enabling column and row addressing of the emitters
34
and apertures
36
, respectively.
A voltage source
44
is provided to apply a voltage differential between emitters
34
and surrounding gate apertures
36
. Application of such voltage differential causes electron streams
46
,
48
, and
50
to be emitted toward phosphor regions
18
,
20
, and
22
respectively. Conductive layer
24
is charged to a potential higher than that applied to gate layer
38
, and thus functions as an anode toward which the emitted electrons accelerate. Once the emitted electrons contact phosphor dots associated with regions
18
,
20
, and
22
light is emitted. As discussed above, the emitters
34
are typically matrix addressable via circuitry. Emitters
34
can thus be selectively activated to display a desired image on the phosphor-coated screen of face plate
12
.
The emitter tips are typically connected to a conductive column line for energizing selected tips. Further, current limiting resistors, typically comprising doped silicon or silicon-containing material are positioned intermediate the emitter tips and column lines to reduce current and avoid burning up the emitter tips. Various aspects of current-limiting resistors and, more generally, field emitter display assemblies are described in the following U.S. Patents, the disclosures of which are incorporated by reference herein: U.S. Pat. Nos. 5,712,534, 5,642,017, 5,644,195, 5,652,181, and 5,663,742.
Referring to
FIGS. 2-7
, various aspects of a field emitter display (FED) assembly in accordance with the prior art are described.
Referring to
FIG. 2
, a substrate
52
is provided and has a plurality of column lines
54
formed or supported thereover. The substrate can comprise any suitable substrate, with exemplary substrate materials being disclosed in one or more of the patents incorporated by reference in this document. Column lines
54
typically comprise a conductive material such as a conductive metal. Exemplary materials can include materials which are disclosed in one or more of the patents incorporated by reference in this document.
Referring to
FIG. 3
, a plurality of resistor islands
56
are formed over the conductive lines. Resistor islands
56
typically comprise a silicon-containing material such as polysilicon. Other materials can be used. The resistor islands can be formed through suitable patterning and etching techniques which are known. As shown in
FIGS. 3 and 6
, individual resistor islands
56
are received entirely within their associated column lines
54
. In addition, a plurality of discrete resistors are formed for each column line.
Referring to
FIGS. 4 and 7
, field emitter regions
58
are formed over resistor islands
56
in accordance with known techniques described in one or more of the above patents. One or more field emitter regions can be formed for each resistor island. The field emitter regions, as perhaps best shown in
FIG. 7
, comprise a plurality of field emitter tips
60
.
Referring to
FIG. 5
, conductive grids or row lines
62
are formed over the substrate in accordance with known techniques. A plurality of windows
64
are provided through grid
62
. The windows expose the individual field emitter regions
58
. Each window defines a single pixel having 100 or more field emitter tips thereon. Each individual resistor island
56
is received completely within their associated illustrated window.
Up to now, problems have existed in such constructions regarding current leakage arcs and shorts between row and column lines, e.g. grid
62
and column lines
54
, even though such lines are spaced and separated by a dielectric insulator material. These shorts and leakage arcs can be most pronounced at the edges of the row and column lines.
Accordingly, this invention arose out of concerns associated with providing improved field emitter display (FED) assemblies and methods of forming field emitter display (FED) assemblies.
SUMMARY OF THE INVENTION
Field emitter display (FED) assemblies and methods of forming field emitter display (FED) assemblies are described. In one embodiment, a substrate is provided having a column line f

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