Electric lamp or space discharge component or device manufacturi – Process – With assembly or disassembly
Reexamination Certificate
2001-04-20
2002-10-15
Ramsey, Kenneth J. (Department: 2879)
Electric lamp or space discharge component or device manufacturi
Process
With assembly or disassembly
C438S020000
Reexamination Certificate
active
06464550
ABSTRACT:
TECHNICAL FIELD
The present invention relates to field emission display backplates and methods of forming field emission display backplates.
BACKGROUND OF THE INVENTION
Field emission displays are utilized in a growing number of applications. Some conventional field emission display configurations include a cathode plate, also referred to as a backplate, having a series of emitter tips fabricated thereon. The emitters are configured to selectively emit electrons toward an opposing screen of a faceplate to produce an image. Such a screen is typically coated with a phosphor to produce an image responsive to emitted electrons striking the screen.
Multiple emitters are typically utilized to excite a single pixel. For example, hundreds of emitters may be utilized for a single pixel. Individual pixels can contain a deposited one of red, green or blue phosphor.
A grid, also commonly referred to as a gate, comprising a conductive material such as metal or polysilicon is preferably formed adjacent and spaced from the emitter tips. The gate is preferably positively charged providing an anode to selectively control the emission of electrons from a corresponding emitter. Inasmuch as the substrate is usually grounded or provided at a lower voltage potential, the selective application of a positive voltage to the gate results in the selective emission of electrons from the corresponding emitter. Further, the corresponding screen of the faceplate may be positively charged to attract emitted electrons. An exemplary field emission display configuration is described in U.S. Pat. No. 5,229,331, assigned to the assignee of the present invention, and incorporated herein by reference.
It has been observed during operation of conventional field emission displays that undesired or spurious electron emission from the emitter to the grid or gate electrode can occur. Such emitted electrons proceed in a substantially horizontal path and are drawn to the gate electrode as opposed to being drawn to the phosphor screen of the faceplate as desired.
Referring to
FIG. 1
a
-
FIG. 1
c,
a process for fabricating an emitter and grid construction of a conventional field emission display backplate fragment
10
is illustrated. Referring specifically to
FIG. 1
a,
fragment
10
includes a bulk substrate
12
. Substrate
12
comprises a monocrystalline silicon wafer, or polysilicon or amorphous silicon on a glass substrate. A layer of first material
13
and a layer of second material
14
are formed within bulk substrate
12
. The first and second layers can be doped with impurities to provide p− semiconductive material
13
and n+ semiconductive material
14
, respectively. A mask
9
is formed over substrate
12
.
Referring to
FIG. 1
b
, isotropic and/or anisotropic etching of the structure of
FIG. 1
a
provides an emitter
11
which extends from a surface of substrate
12
. The etch is timed such that emitter
11
typically comprises substantially n+ semiconductive material
14
.
Referring to
FIG. 1
c
, a conformal layer of insulative material
18
is deposited over substrate material
13
and emitter
11
following the formation of emitter
11
. Thereafter, conductive material
16
having surfaces
17
is formed over the layer of insulative material
18
. Field emission display backplate fragment
10
may next undergo chemical-mechanical polishing to remove portions of the conductive material and the conformal insulating material which extends beyond emitter
11
as described in U.S. Pat. No. 5,229,331. The chemical-mechanical polishing step exposes the insulative layer about emitter
11
. Wet etching of the insulative layer forms the depicted regions of insulative material
18
and exposes emitter
11
.
An electrical field is generated intermediate surfaces
17
of grid
16
and emitter
11
to provide electron emission from emitter
11
through an opening
15
within grid
16
. During operation, spurious electrons may be drawn in a substantially horizontal direction towards grid
16
as opposed to a direction through opening
15
. Such is undesired. This problem is particularly acute in applications where the spacing intermediate grid surfaces
17
and emitter
11
is reduced to provide a field emission display backplate structure
10
which is operable with lower turn-on voltages.
Referring to
FIG. 2
, a conventional structure utilized to reduce the emission of spurious electrons from emitter
11
to grid
16
a
is illustrated. More specifically, increasing the spacing intermediate the outer surface of emitter
11
and surfaces
17
of grid
16
reduces the flow of such spurious electrons to grid
16
.
Conventional field emission display fragment
10
a
can be formed utilizing a reflow processing step. More specifically, following the formation of the conformal insulative layer, a reflow process step is conducted to reduce the slope of portions of the insulative layer over emitter
11
. Thereafter, a conductive layer is deposited over the reflowed insulative layer to form grid
16
a
. Such provides surfaces
17
a
of grid
16
a
having reduced slopes compared with grid surfaces
17
shown in
FIG. 1
c
and represented as dashed lines. In particular, the depicted grid
16
a
includes surfaces
17
a
which are pulled back from emitter
11
compared with surfaces
17
of grid
16
of
FIG. 1
c
. Fragment
10
a
of
FIG. 2
provides reduced spurious electron emission from tip
11
to grid
16
a
compared with the emission of spurious electrons from tip
11
to grid
16
of
FIG. 1
c.
However, the described reflow processing technique of the conformal insulative layer has some disadvantages with respect to field emission display backplate processing. For example, the reflow temperature of the insulative material may exceed the strain point of some glass substrates resulting in damage to the structure. Further, the reflowed insulative layer may have a non-uniform thickness across the substrate because of possible varied temperatures across the substrate during the reflow processing step. Also, reflow processing techniques are often difficult to implement in arrangements having a large number of tips in close proximity to one another because of increased surface tension. Numerous tips are typically provided within field emission display backplates to reduce non-uniform characteristics of individual ones of the tips. In addition, opening
15
formed within grid
16
a
is sensitive to chemical-mechanical polishing inasmuch as grid
16
a
has been pulled back from tips
11
.
Therefore, there exists a need to provide improved field emission display backplate structures and processing methodologies of the same which overcome the problems associated with the prior art.
SUMMARY OF THE INVENTION
The present invention includes field emission display backplates and methods of forming field emission display backplates. According to a first aspect, a field emission display backplate includes a substrate having a surface and an emitter which extends from the surface of the substrate. Further, an anode having an upper surface, a lower surface, and an opening surface, is formed spaced from the emitter. The opening surface defines an opening aligned with the emitter and the opening surface includes a first portion which curves outward relative to the anode and a second portion which curves inward relative to the anode.
According to some aspects, the emitter has a surface including an inner surface portion which curves outward relative to the emitter and an outer surface portion which curves inward relative to the emitter. The outer surface of the emitter can be parallel to the opening surface of the anode. The emitter has a length in a direction substantially orthogonal to the surface of the substrate. The inner portion of the emitter has a length comprising approximately 15 percent to 95 percent of the length of the emitter according to some aspects.
The present invention includes other aspects wherein the emitter includes an inner portion comprising a first doping type semiconductive material and an outer
Micro)n Technology, Inc.
Ramsey Kenneth J.
Wells St. John P.S.
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