Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
1999-12-13
2001-10-09
Bowers, Charles (Department: 2813)
Metal working
Method of mechanical manufacture
Electrical device making
C029S830000, C438S612000, C438S613000, C438S614000, C427S096400
Reexamination Certificate
active
06298551
ABSTRACT:
BACKGROUND OF THE INVENTION
Ball grid array (BGA) technology provides a high density of interconnections per unit area, but mismatches of coefficients of thermal expansion (CTEs) occur when ceramic or polymer BGA substrates and printed circuit boards are joined and often result in cracked solder joints, especially as the size of the substrates and temperature ranges are increased. In column grid array (CGA) techniques and other BGA techniques, a eutectic solder is applied to printed circuit board and multi-chip module array pads and the resulting joint is soldered to a higher temperature solder column or ball which does not melt. Both BGA and CGA structures can be inflexible and vulnerable to damage. For various types of BGA and CGA, increases in reliability are attempted by elaborate under-filling of the structures with polymer glues to reinforce the interfaces and reduce the effects of the CTE mismatch on the solder joints. The polymer glues, however, impair repairability because of the difficulty in removing the glues after hardening. Furthermore, these types of structures require two separate solder steps, are more expensive than conventional solder structures, and require more vertical space due to increased height of the joints.
One conventional micro ball grid array interface technique for attaching a semiconductor circuit chip directly to a substrate is to use a series of solder bumps clustered at the center of the chip to constrain the area over which stresses between differing coefficients of thermal expansion occur. In this embodiment, chips have their pads reconfigured and solder micro bumps are applied over the reconfigured pads. In one embodiment, ball grid array processes are used with the temperature range being constrained during device operation to 30° C. to 70° C. in an effort to avoid CTE stress effects. In another ball grid array interface technique, the area where the chip faces the printed circuit board or substrate is not used for direct interconnection. Instead, metallization is routed from the chip to adjacent support structures which then have solder ball connections. This technique can create size and pin count limitations as well as electrical parasitic effects.
SUMMARY OF THE INVENTION
It would be desirable to have a method for providing highly compliant electrically conductive interconnections for structures having differing coefficients of thermal expansion and to have a base pad and metallization contact area with long term reliability (i.e. without cracks or breaks) even under thermal and material stress conditions without the need for rerouting chip pads to the center of a chip or to an adjacent support structure.
In one embodiment of the present invention, a method and structure electrically interconnect materials having different coefficients of thermal expansion. A “floating pad” structure is used to increase reliability by providing stress and thermal accommodation of the two materials and permitting movement of the floating pad independent of the base pad. The invention includes a floating pad interface structure that is connected to a semiconductor chip's original pad by means of micro extensions that provide stress relief for different coefficients of thermal expansion. The floating pad interface structures can include a single pad and extension or several extensions in situations wherein a single extension is not sufficient for extreme thermal stress/strain situations. The present invention provides a structure that accommodates thermal and material stresses without submitting the via interconnect areas to forces that can crack vias or break connections at the chip pads. The floating pads permit movement independent of a semiconductor while providing electrical interconnections through selected materials that are specifically patterned to provide low forces at the via areas and thus accommodate differential thermal stresses which may be caused by large CTE differences.
In another embodiment of the present invention a micro structure interface is provided that is solderable and forms an electronic interconnection without requiring pressure. The interconnections can be held in position prior to application by an interposer that provides ease of assembly and surface mount technology self-alignment capability. A conductive contact area interface may comprise: at least one electrically conductive first contact area; at least one electrically conductive second contact area facing and being substantially aligned with the at least one first contact area; and at least one interface structure coupled between the at least one first contact area and the at least one second contact area. The at least one interface structure comprises at least one electrical conductor having a partially open interior to form a compliant joint between the at least one first contact area and the at least one second contact area.
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Gorowitz Bernard
Whitmore Barry Scott
Wojnarowski Robert John
Agosti Ann M.
Bowers Charles
Breedlove Jill M.
General Electric Company
Smoot Stephen W.
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