Methods of forming capacitors methods of forming DRAM cells,...

Details Methods of forming capacitors methods of forming DRAM cells,... Methods of forming capacitors methods of forming DRAM cells,...

1998-11-10

2001-01-23

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S255000, C438S398000

Reexamination Certificate

active

06177328

ABSTRACT:

TECHNICAL FIELD
This invention pertains to semiconductor capacitor constructions, dynamic random access memory (DRAM) cell constructions, methods of forming semiconductor capacitor constructions, methods of forming DRAM cell constructions, and to integrated circuits incorporating capacitor structures and DRAM cell structures.
BACKGROUND OF THE INVENTION
A DRAM is a commonly used semiconductor device comprising a capacitor and a transistor. A continuous challenge in the semiconductor industry is to decrease the vertical and/or horizontal size of semiconductor devices, such as DRAMs and capacitors. A limitation on the minimal horizontal footprint of capacitor constructions is impacted by the resolution of a photolithographic etch during fabrication of the capacitor constructions. Although this resolution is generally improving, at any given time there is a minimum photolithographic feature dimension of which a fabrication process is capable. It would be desirable to) form capacitors at least some portions of which have a cross-sectional minimum dimension of less than the minimum capable photolithographic feature dimension of a given fabrication process.
A problem in the semiconductor industry is mask misalignment. Mask misalignment during device fabrication can lead to inoperative devices. Accordingly, it is desirable to design device-fabrication processes which can compensate for mask misalignment.
SUMMARY OF THE INVENTION
The invention encompasses DRAM cell structures, capacitor structures, methods of forming capacitor structures, methods of forming capacitor structures, and systems incorporating capacitor structures and DRAM structures.
The invention includes methods of forming capacitors wherein an opening is formed within an insulative layer and over a node location. A spacer is formed within the opening to narrow the opening, with the spacer having inner and outer surfaces, with the inner surface forming a periphery of the narrowed opening, with the spacer having an bottom base surface, with the base surface being above the node location. A portion of the insulative layer is removed from proximate the outer surface to expose at least a portion of the outer surface. A storage node layer is formed in electrical connection with the node location, along the spacer inner surface, and along the exposed spacer outer surface. A dielectric layer is formed operatively proximate the storage node layer. A cell plate layer is formed operatively proximate the dielectric layer and the storage node layer.
The invention also includes capacitor constructions. Such include a node location within a substrate; an insulative layer over the substrate; a contact opening extending through the insulative layer to the node location; a conductive spacer within the contact opening and narrowing at least a portion of the contact opening; the conductive spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed portion of the contact opening; a storage node layer in physical contact with the node location and extending along both of the inner and outer surfaces of the conductive spacer, the storage node layer and conductive spacer together forming a capacitor storage node; a dielectric layer operatively proximate the storage node; and a cell plate layer operatively proximate the storage node and the dielectric layer.
The invention further encompasses DRAM cell structures and microprocessor controlled systems incorporating the above-described capacitors.


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