Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2001-11-20
2002-12-10
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S398000
Reexamination Certificate
active
06492243
ABSTRACT:
TECHNICAL FIELD
The present invention relates to methods of forming capacitors and to resultant capacitor structures.
BACKGROUND OF THE INVENTION
As integrated circuitry dimensions continue to shrink, challenges are posed with respect to the techniques through which integrated circuit structures are formed. For example, with very small device dimensions, unwanted conductive particles present during fabrication can cause undesired shorting should they come into contact with, and not be adequately removed from integrated circuitry being formed. One type of integrated circuit structure is a capacitor. Such capacitors are typically used in dynamic random access memory circuitry. Undesired shorting can take place if such conductive particles are allowed to undesirably contact the capacitor storage nodes of such capacitors.
Accordingly, this invention arose out of concerns associated with providing improved methods of forming integrated circuitry which reduce the risk of undesired particles shorting the resultant integrated circuitry structures. In particular, this invention arose out of concerns associated with providing improved methods of forming capacitors, and resultant capacitor constructions.
SUMMARY OF THE INVENTION
Methods of forming capacitors and resultant capacitor structures are described. In one embodiment, a capacitor storage node layer is formed over a substrate and has an uppermost rim defining an opening into an interior volume. At least a portion of the rim is capped by forming a material which is different from the capacitor storage node layer over the rim portion. After the rim is capped, a capacitor dielectric region and a cell electrode layer are formed over the storage node layer.
In another embodiment, a capacitor storage node layer is formed within a container which is received within an insulative material. A capacitor storage node layer is formed within the container and has an outer surface. A layer of material is formed within less than the entire capacitor container and covers less than the entire capacitor storage node layer outer surface. The layer of material comprises a material which is different from the insulative material within which the capacitor container is formed. After the capacitor storage node layer and the layer of material are formed, a capacitor dielectric functioning region is formed which is discrete from the layer of material and operably proximate at least a portion of the capacitor storage node layer outer surface. A cell electrode layer is formed over the dielectric functioning region and the layer of material.
In another embodiment, a capacitor container is formed within an insulative material over a substrate. A capacitor storage node is formed within the container and has an uppermost surface and a side surface joined therewith. A protective cap is formed over the uppermost surface. A dielectric layer is formed over at least some of the side surface and protective cap. A cell electrode layer is formed over the side surface of the capacitor storage node.
REFERENCES:
patent: 5338700 (1994-08-01), Dennison et al.
patent: 5905280 (1999-05-01), Liu et al.
patent: 5981333 (1999-11-01), Parekh et al.
patent: 6150211 (2000-11-01), Zahurak
Fahmy Wael
Micro)n Technology, Inc.
Pham Thanh V
Wells St. John P.S.
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