Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
2008-01-15
2009-06-30
Chambliss, Alonzo (Department: 2892)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
C438S622000, C257S758000, C257S774000, C257S776000, C257SE23143, C257SE23145
Reexamination Certificate
active
07553703
ABSTRACT:
Semiconductor devices having conductive lines with extended ends and methods of extending conductive line ends by a variable distance are disclosed. An end of a first conductive feature of an interconnect structure is extended by a first distance, and an end of a second conductive feature of the interconnect structure is extended by a second distance, the second distance being different than the first distance. Ends of conductive features that are positioned close to adjacent conductive features are preferably not extended.
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Herold Klaus
Kaltalioglu Erdem
Chambliss Alonzo
Infineon - Technologies AG
Slater & Matsil L.L.P.
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