Methods of forming a vertical field-effect transistor and a semi

Details Methods of forming a vertical field-effect transistor and a semi Methods of forming a vertical field-effect transistor and a semi

1992-07-28

1994-11-15

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 29, 437 38, 437 59, 437203, H01L 2170, H01L 2700

Patent

active

053648102

ABSTRACT:
The disclosure includes a vertical field-effect transistor (115) with a laterally recessed channel region (92), a vertical field-effect transistor (116) having a graded diffusion junction (31), a static random access memory cell (110) having a vertical n-channel field-effect transistor (116) and a vertical p-channel field-effect transistor (115) and methods of forming them. In one embodiment, a six-transistor static random access memory cell (110) has two pass transistors (111 and 114), which are planar n-channel field-effect transistors, two latch transistors (113 and 116), which are vertical n-channel field-effect transistors with drain regions having graded diffusion junctions (31), and two load transistors (112 and 115), which are vertical p-channel thin-film field-effect transistors having laterally recessed channel regions (92).

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