Methods of fabrication of wafer-level vacuum packaged devices

Details Methods of fabrication of wafer-level vacuum packaged devices Methods of fabrication of wafer-level vacuum packaged devices

2006-08-07

2008-07-22

Wilczewski, M. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Insulating material

C257S678000, C257S701000, C257S682000, C438S125000

Reexamination Certificate

active

07402905

ABSTRACT:
An hermetic, gas filled or vacuum package device and method of making a vacuum package device. The device includes a device layer having one or more Micro Electro-Mechanical Systems (MEMS) devices. The device layer includes one or more electrical leads coupled to the one or more MEMS devices. The device also includes a first wafer having one or more silicon pins, wherein a first surface of the first wafer is bonded to a first surface of the device layer in such a manner that the one or more silicon pins are in electrical communication with the electrical leads. A second wafer, which may also have one or more silicon pins, is bonded to a second surface of the device layer. The first and second wafers are formed of borosilicate glass and the device layer is formed of silicon.

REFERENCES:
patent: 2005/0006738 (2005-01-01), Schaper et al.
patent: 2005/0085053 (2005-04-01), Chen et al.
patent: 2005/0233543 (2005-10-01), Wei et al.
patent: 2006/0110893 (2006-05-01), Quenzer et al.
patent: 2007/0023890 (2007-02-01), Haluzak et al.

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