Methods of fabricating vertical field effect transistors by...

Details Methods of fabricating vertical field effect transistors by... Methods of fabricating vertical field effect transistors by...

2001-11-06

2003-12-16

Loke, Steven (Department: 2811)

Semiconductor device manufacturing: process

Making regenerative-type switching device

Having field effect structure

C438S212000, C438S268000

Reexamination Certificate

active

06664143

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to microelectronic devices and fabrication methods therefor, and more particularly to microelectronic vertical field effect transistors and fabrication methods therefor.
Field Effect Transistors (FET), also referred to as Metal Oxide Semiconductor Field Effect Transistors (MOSFET) or Complementary Metal Oxide Semiconductor (CMOS) transistors, are widely used in integrated circuit devices including logic, memory and/or microprocessor devices that are used in consumer and/or industrial applications. As the integration density of integrated circuit field effect transistors continues to increase, it may be desirable to continue to shrink the dimensions of the field effect transistors. For example, present day FETs may be fabricated with a minimum device feature size of about 0.18 to about 0.25 &mgr;m. However,
The International Roadmap for Semiconductors,
published by International SEMATECH at http://www.itrs.net/1999 SIA Roadmap/Home.htm, predicts that the minimum gate length will reach 35 nm in 10-15 years.
Conventionally, features of integrated circuit FETs may be formed on a microelectronic substrate, such as silicon semiconductor substrate, using photolithography and etching. Unfortunately, as the minimum feature size scales into the sub-0.1 &mgr;m region, it may be increasingly difficult to define such small features using traditional lithography and etching. Although improved nano-lithography techniques may be developed, it still may be difficult to reliably define features as small as 35 nm or smaller in a controllable and cost-effective way using lithography, to allow mass production. Moreover, from a device physics point of view, as the dimensions of FETs continues to shrink, the suppression of short channel effects may become increasingly difficult.
In attempts to reduce short channel effects, planar fully depleted ultra-thin body Semiconductor-On-Insulator (SOI) FETs have been developed. For example, using a semiconductor-on-insulator substrate and etchback or oxide thinning, ultra-thin SOI channels may be obtained. See, for example, Choi et al.,
Ultra
-
Thin Body SOI MOSFET for Deep
-
Sub
-
Tenth Micron Era,
Paper 3.7.1, IEDM, 1999, pp. 919-921. Other approaches have deposited a thin layer of amorphous silicon or silicon germanium alloy on a planar oxide surface, followed by lateral solid-state crystallization. See, Yeo et al.,
Nanoscale Ultra
-
Thin
-
Body Silicon
-
On
-
Insulator P
-
MOSFET with a SiGe/Si Heterostructure Channel,
IEEE Electron Device Letters, Vol. 21, No. 4, 2000, pp. 161-163. Unfortunately, although planar fully depleted ultra thin body devices may be capable of reducing short channel effects, it may be difficult to further increase the integration density and/or performance of these devices, because the gate may still be defined by lithography.
Double gate and/or surround gate FETs also have been proposed to reduce short channel effects. A double/surround gate FET may include a thin channel that is controlled by both a front gate and a back gate. Short channel effects may be suppressed because the two gates can be effective in terminating drain field lines and preventing the drain potential from impacting the source. Double gate devices may be extended to provide surround gate devices in which the gate wraps around the channel. As shown by computer simulations, in order to effectively suppress the short channel effects in a double gate MOSFET, the channel thickness may need to be as thin as one-half to one-third of the gate length. See, for example, Wong et al.,
Device Design Considerations for Double
-
Gate, Ground
-
plane, and Single
-
Gated Ultra
-
Thin SOI MOSFET's at the
25
nm Channel Length Generation,
IEDM, 1998, pp. 407-410.
FETs including double/surround gate FETs may be grouped into two categories based on the channel orientation. In horizontal devices, carrier conduction from source to drain through the channel occurs in a direction that is generally parallel to the face of the microelectronic substrate. In contrast, in vertical devices, carrier conduction from source to drain through the channel occurs in the vertical direction, generally orthogonal to the face of the microelectronic substrate.
In horizontal approaches for fabricating double/surround gate FETs, the gate length may be defined by lithography, and the formation of a back gate beneath the thin channel and its accurate alignment to the top gate may present challenges. See, for example, the publications to Tanaka et al., entitled
Ultrafast Operation of V
th
-
Adjusted p
+-
n+Double
-
Gate SOI MOSFETs,
IEEE Electron Device Letters. Vol. 15, No. 10, October 1994, pp. 386-388; Colinge et al., entitled
Silicon
-
on
-
Insulator “Gate
-
All
-
Around Device”,
IEDM, 1990, pp. 595-598; Leobandung et al., entitled
Wire
-
Channel and Wrap
-
Around
-
Gate Metal
-
Oxide
-
Semiconductor Field
-
Effect Transistors With a Significant Reduction of Short Channel Effects,
Journal of Vacuum Science Technology B, 15(6), November/December 1997, pp. 2791-2794; Hisamoto et al., entitled
A Folded
-
Channel MOSFET for Deep
-
sub
-
tenth Micron Era,
IEDM, 1998, pp. 1032-1034; and Lee et al., entitled
Super Self
-
Aligned Double
-
Gate
(
SSDG
)
MOSFETs Utilizing Oxidation Rate Difference and Selective Epitaxy,
IEDM, 1999, pp. 71-74.
In contrast, in vertical devices, the fabrication of the double/surround gate structures may be more straightforward because both the front and back gates can be formed simultaneously. Vertical FETs also may be fabricated with a higher integration density, because carrier conduction occurs orthogonal to the substrate face. See, Takato et al., entitled
High Performance CMOS Surrounding Gate Transistor
(
SGT
)
for Ultra High Density LSIs,
IEDM, 1988, pp. 222-225; Risch et al., entitled
Vertical MOS Transistors With
70
nm Channel Length,
IEEE Transactions on Electron Devices, Vol. 43, No. 9, September 1996, pp. 1495-1498; Auth et al., entitled
Scaling Theory for Cylindrical, Fully
-
Depleted, Surrounding
-
Gate MOSFET's,
IEEE Electron Device Letters, Vol. 18, No. 2, February 1997, pp. 74-76; and Yang et al., entitled 25-
nm p
-
Channel Vertical MOSFET's With SiGeC Source
-
Drains,
IEEE Electron Device Letters, Vol. 20, No. 6, June 1999, pp. 301-303. In vertical devices, the gate length is usually defined by thin-film deposition. However, the lithography actually may be more difficult, because the channel thickness, which may be about one-third of the gate length, generally is lithography-dependent.
A vertical replacement gate MOSFET also is described in a publication by Hergenrother et al., entitled
The Vertical Replacement
-
Gate
(
VRG
)
MOSFET: A
50-
nm Vertical MOSFET With Lithography
-
Independent Gate Length,
IDEM, 1999, p. 75, the disclosure of which is hereby incorporated herein by reference in its entirety. As described in the abstract of Hergenrother et al., the VRG MOSFET is the first MOSFET ever built that combines 1) a gate length controlled precisely through a deposited film thickness, independently of lithography and etch, and 2) a high-quality gate oxide grown on a single-crystal Si channel. In addition to this unique combination, the VRG-MOSFET includes a self-aligned S/D formed by solid source diffusion (SSD) and small parasitic overlap, junction, and S/D capacitances. The drive current per &mgr;m of coded width is significantly higher than that of advanced planar MOSFETs because each rectangular device pillar (with a thickness of minimum lithographic dimension) contains two MOSFETs driving in parallel. All of this is achieved using current manufacturing methods, materials, and tools, and competitive devices with 50-nm gate lengths (L
G
) having been demonstrated without advanced lithography. See the Hergenrother et al. abstract.
As also described in the “Device Fabrication” section of Hergenrother et al., in the VRG process, arsenic was implanted into an epi Si wafer to form the device drain and a thin oxide diffusion barrier was deposited. A PSG

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