Semiconductor device manufacturing: process – Electron emitter manufacture
Reexamination Certificate
2003-04-01
2004-02-24
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Electron emitter manufacture
C438S022000, C438S047000, C438S142000, C438S478000
Reexamination Certificate
active
06696306
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of fabricating a layered structure using a film deposition technique such as metal-organic chemical vapor deposition (MOCVD) and a method of fabricating a semiconductor device including the layered structure.
High electron mobility transistors (HEMTs) using a two-dimensional electron gas (2DEG) quantized at a heterojunction interface between different types of compound semiconductor layers are currently used in high-power devices such as microwave devices because they have high performance such as high-speed/high-frequency operating characteristics and low-noise properties. Especially, gallium nitride (GaN) based HEMTs (more specifically, GaN/AlGaN-based HEMTs) having a heterojunction between a GaN channel layer and an n-type Al
x
Ga
1−x
N (0<x<1) electron supply layer show a variety of excellent electrical characteristics and are extensively studied.
MOCVD has been widely used for forming a heterojunction by epitaxially growing the compound semiconductor layers on a substrate. MOCVD is a film deposition technique for epitaxially growing a desired crystalline layer by supplying predetermined source gases successively onto a substrate at a predetermined high temperature.
The film deposition technique using MOCVD, however, has the following problems.
Suppose that a crystalline GaN layer and a crystalline Al
x
Ga
1−x
N (0<x<1) layer are successively grown on a substrate to form a layered structure, using MOCVD. When the temperature of the layered structure drops in a cooling step after the crystal growth step, an unwanted internal stress occurs in an exposed surface of the Al
x
Ga
1−x
N layer, which results from a difference between thermal expansion coefficients (linear expansion coefficients) of the Al
x
Ga
1−x
N layer and the GaN layer.
An inventor associated with this patent application observed atomic force microscopy (AFM) images of the surface of the Al
x
Ga
1−x
N layer showing a cracked structure at room temperature after the cooling step, as shown in FIG.
11
. The surface of the Al
x
Ga
1−x
N layer probably is supposed to take on flat and smooth structure immediately after the crystal growth step and before the cooling step, while it is impossible to carry out the AFM observation under such the condition.
FIG. 11
shows an AFM image obtained by scanning an area of 1-&mgr;m square of the Al
x
Ga
1−x
N layer which was cooled with its surface exposed, at a scanning rate of about 1.2 Hz. White areas
11
a
in the figure are surfaces that can be in contact with an AFM probe and are used as a reference surface. Black areas
11
c
in the figure are depressed by about 10 nm with reference to the white areas
11
a
. Gray areas
11
b
in the figure are also depressed by less than 10 nm with reference to the white areas
11
a
, and the depth of the gray areas
11
b
are shallower than the depth of the black areas
11
c
. As shown in
FIG. 11
, the Al
x
Ga
1−x
N layer has a very rough surface with a large number of depressed areas. More precisely, the cracks in the surface of the Al
x
Ga
1−x
N layer have a depth ranging approximately from 3 nm to 7 nm and a width ranging approximately from 10 nm to 30 nm.
Accordingly, if a gate electrode is disposed on the Al
x
Ga
1—x
N layer, as in a GaN-based HEMT, for instance, the uneven contact surface between the Al
x
Ga
1−x
N layer and the gate electrode obstructs the normal FET operation, making it impossible to accurately evaluate the electrical characteristics of the device.
In addition, the uneven contact surface weakens the adhesion between the Al
x
Ga
1−x
N layer and the gate electrode, raising the fear that the gate electrode is detached.
Reference
1
(Stacia Keller et al. “Gallium Nitride Based High Power Heterojunction Field Effect Transistor: Process Development and Present Status at UCSB”, IEEE Transaction on Electron Devices, vol. 48, No. 3, pp. 552-559, March 2001) discloses that the formation of crystal grains leading to the cracked structure in the surface of the Al
x
Ga
1−x
N layer shown in
FIG. 11
can be suppressed by performing MOCVD for growing the crystalline Al
x
Ga
1−x
N layer with a low flow of ammonia (NH
3
) gas and a high surface mobility of metal species.
However, it is difficult to flatten the surface of the Al
x
Ga
1−x
N layer by optimizing the flow rate of ammonia in MOCVD, which has high apparatus dependence.
The flow rate of ammonia disclosed in Reference
1
is not always the optimum value for all MOCVD apparatuses. Moreover, there is a possibility that the optimum value of a flow rate of ammonia may be beyond the controllability of the apparatus. Therefore, it cannot be said that the technique disclosed in Reference
1
is a general flattening method.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of fabricating a layered structure, which enables to flatten the surface of the layered structure formed by growing crystals, and a method of fabricating a semiconductor device including the layered structure.
According to the present invention, a method of fabricating a layered structure including a substrate, a first semiconductor layer with a first thermal expansion coefficient &agr;
A
, and a second semiconductor layer with a second thermal expansion coefficient &agr;
b
deposited on the first semiconductor layer, wherein &agr;
A
is greater than &agr;
B
or smaller than &agr;
B
, includes: forming the first semiconductor layer, the second semiconductor layer, and a third semiconductor layer with a third thermal expansion coefficient &agr;
C
in this order on the substrate at a first temperature using a film deposition technique, thereby forming a structural body including the substrate and the first to third semiconductor layers, wherein &agr;
C
is greater than &agr;
B
if &agr;
A
is greater than &agr;
B
or &agr;
C
is smaller than &agr;
B
if &agr;
A
is smaller than &agr;
B
; cooling the structural body to a second temperature, which is lower than the first temperature; and removing the third semiconductor layer from the structural body to expose the second semiconductor layer.
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Peng, L. H. et al, “Structure Asymmetry Effects in the Optical Gain of Piezostrained InGaN Quantum Wells”, IEEE Journal of Selected Topics in Quantum Eelctronics, vol. 5, No. 3, May/Jun. 1999, pp. 1756-1764.*
Robins, L.H. et al, “Optical and Structural studies of compositional inhomgeneity on strain-relaxed indium gallium nitride films”, IEEE 2000, pp. 507-512.*
Stacia Keller et al. “Gallium Nitride Based High Power Heterojunction Field Effect Transistor: Process Development and Present Status at UCSB”, IEEE Transaction on Electron Devices, vol. 48, No. 3, pp. 552-559, Mar. 2001.
Lebentritt Michael S.
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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