Methods of fabricating integrated circuitry

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S114000

Reexamination Certificate

active

07078267

ABSTRACT:
A substrate including a plurality of integrated circuitry die is fabricated or otherwise provided. The individual die have bond pads. A passivation layer comprising a silicone material is formed over the bond pads. Openings are formed through the silicone material to the bond pads. After the openings are formed, the die are singulated from the substrate. In one implementation, a method of fabricating integrated circuitry includes providing a substrate comprising a plurality of integrated circuitry die. Individual of the die have bond pads. A first blanket passivation layer is formed over the substrate in contact with the bond pads. A different second blanket passivation layer comprising silicone material is formed over the first passivation layer. Openings are formed through the first and second passivation layers to the bond pads. After the openings are formed, the die are singulated from the substrate. Other aspects and implementations are contemplated.

REFERENCES:
patent: 4328262 (1982-05-01), Kurahashi et al.
patent: 4505029 (1985-03-01), Owyang et al.
patent: 4982265 (1991-01-01), Watanabe et al.
patent: 4988403 (1991-01-01), Matuo
patent: 5013689 (1991-05-01), Yamamoto et al.
patent: 5097317 (1992-03-01), Fujimoto et al.
patent: 5136364 (1992-08-01), Byrne
patent: 5171716 (1992-12-01), Cagan et al.
patent: 5180691 (1993-01-01), Adachi et al.
patent: 5287003 (1994-02-01), Van Andel et al.
patent: 5406117 (1995-04-01), Dlugokecki et al.
patent: 5563102 (1996-10-01), Michael
patent: 5600151 (1997-02-01), Adachi et al.
patent: 5693565 (1997-12-01), Camilletti et al.
patent: 5825078 (1998-10-01), Michael
patent: 5834844 (1998-11-01), Akagawa et al.
patent: 5888846 (1999-03-01), Miyata et al.
patent: 6075290 (2000-06-01), Schaefer et al.
patent: 6127099 (2000-10-01), Shinohara
patent: 6143668 (2000-11-01), Dass et al.
patent: 6313044 (2001-11-01), Lee
patent: 6368896 (2002-04-01), Farnworth et al.
patent: 6383893 (2002-05-01), Begle et al.
patent: 6388337 (2002-05-01), Michael et al.
patent: 6410414 (2002-06-01), Lee
patent: 6492200 (2002-12-01), Park et al.
patent: 6501014 (2002-12-01), Kubota et al.
patent: 6539624 (2003-04-01), Kung et al.
patent: 6576990 (2003-06-01), Flesher et al.
patent: 6586276 (2003-07-01), Towle et al.
patent: 6586323 (2003-07-01), Fan et al.
patent: 6617674 (2003-09-01), Becker et al.
patent: 6646354 (2003-11-01), Cobbley et al.
patent: 6696317 (2004-02-01), Honda
patent: 6709893 (2004-03-01), Moden et al.
patent: 6709896 (2004-03-01), Cobbley et al.
patent: 6743664 (2004-06-01), Liang et al.
patent: 6783692 (2004-08-01), Bhagwagar
patent: 6803303 (2004-10-01), Hiatt et al.
patent: 6858927 (2005-02-01), Prindiville et al.
patent: 6887771 (2005-05-01), Kobayashi
patent: 6896760 (2005-05-01), Connell et al.
patent: 6900079 (2005-05-01), Kinsman et al.
patent: 6940177 (2005-09-01), Dent et al.
patent: 2003/0025188 (2003-02-01), Farnworth et al.
patent: 2003/0027918 (2003-02-01), Tsutsumi et al.
patent: 2003/0030132 (2003-02-01), Lee et al.
patent: 2003/0082925 (2003-05-01), Yano et al.
patent: 2003/0143794 (2003-07-01), Nakamura et al.
patent: 2003/0153103 (2003-08-01), Perry
patent: 2003/0230799 (2003-12-01), Yee et al.
Garrou et al.,Stress-Buffer and Passivation Processes for Si and GaAs IC's and Passive Components. . . , IEEE Transactions on Advanced Packaging, vol. 22, No. 3, pp. 487-498 (Aug. 1999).
Miura,Spherical Filler-Induced Damage in IC Plastic Packages,Advances in Electronic Packaging, vol. 26-1, pp. 167-172 (1999).
Yalamanchili et al.,Filler Induced Metal Crush Failure Mechanism in Plastic Encapsulated Devices,IEEE 37thAnnual International Reliability Physics Symposium, San Diego, California, pp. 341-346 (1999).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods of fabricating integrated circuitry does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of fabricating integrated circuitry, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of fabricating integrated circuitry will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3589237

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.