Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2007-01-02
2007-01-02
Mai, Son L. (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185170, C365S185200
Reexamination Certificate
active
10918966
ABSTRACT:
Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main cell array region are provided. A first erasure voltage is applied to a plurality of main control gate electrodes in the main cell array region. The plurality of main control gate electrodes include a first outermost main control gate electrode adjacent to the first dummy cell array region and a second outermost main control gate electrode adjacent to the second dummy cell array region. A second erasure voltage is applied to an integrated circuit substrate in the main cell array region. The second erasure voltage is greater than the first erasure voltage. A third erasure voltage is applied to a first inner dummy control gate electrode adjacent to the first outermost main control gate electrode and a second inner dummy control gate electrode adjacent to the second outermost main control gate electrode. The third erasure voltage is less than the second erasure voltage. Related devices are also provided.
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Han Jung-In
Lee Chang-Hyun
Park Kwang-Won
Mai Son L.
Myers Bigel & Sibley & Sajovec
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