Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Computer or peripheral device
Reexamination Certificate
2007-07-24
2007-07-24
Shah, Kamini (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Computer or peripheral device
C702S058000, C702S059000, C702S185000, C716S030000
Reexamination Certificate
active
10407280
ABSTRACT:
Methods of estimating the susceptibility to single event upsets (SEUs) of a design implemented in an FPGA. In an FPGA, many of the configuration memory cells could change state in response to an SEU without affecting the functionality of a design implemented in the FPGA. According to the methods of the invention, the number of “care bits” (bits associated with resources actually used in the design) is determined. The number of care bits as a proportion of the total number of configuration memory cells in the FPGA determines the “SEU Probability Impact” (SEUPI) value. The “Mean Time Between Upsets” (MTBU) value is an estimate of how much time will elapse, on average, before one of the configuration memory cells in the FPGA is affected by an SEU. To obtain the “Mean Time Between Failures” for the design implemented in the FPGA, the MTBU value is divided by the SEUPI value.
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Blodget Brandon J.
Carmichael Carl H.
McMillan Scott P.
Patterson Cameron D.
Sundararajan Prasanna
Cartier Lois D.
Lo Suzanne
Shah Kamini
Xilinx , Inc.
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