Methods of electroplating solder bumps of uniform height on inte

Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area

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205123, C25D 502

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active

061172995

ABSTRACT:
Methods of electroplating solder bumps of uniform height on integrated circuit substrates include the steps of drawing plating current through an integrated circuit wafer by electrically shorting an integrated circuit's ground, power and signal pads together using an ultra-thin plating base layer (e.g., <0.075 .mu.m thick) and then using a backside wafer contact to draw electroplating current along parallel paths which extend through the ground and signal pads and into the substrate. The ground pads are preferably electrically coupled to the substrate at substrate contact regions (e.g., N + or P + diffusion regions) and the signal pads are preferably electrically coupled to the substrate through active semiconductor devices (e.g., FETs, BJTs, . . . ) to which the signal pads are attached. Plating current is preferably drawn in parallel through an integrated circuit's active semiconductor devices and substrate contact regions. The combined contributions of the plating currents drawn through the substrate contact regions and the active semiconductor devices is sufficient to maintain the plating base layer and underlying pads at uniform potentials even though the plating base layer has a preferred thickness of less than about 0.075 .mu.m. These uniform and typically non-zero potentials cause the rates of electroplating to be highly uniform across the wafer by limiting lateral current flow through the plating base layer. The uniformity of the electroplated solder bumps can also be enhanced by using high density controlled collapse chip connection (C4) ("flip-chip") technologies and by interspersing the ground and signal pads on each "flip-chip" so that each signal pad has at least one ground pad as a nearest neighbor.

REFERENCES:
patent: 3625837 (1971-12-01), Nelson et al.
patent: 3760238 (1973-09-01), Hamer et al.
patent: 4142202 (1979-02-01), Csillag et al.
patent: 4205099 (1980-05-01), Jones et al.
patent: 4784972 (1988-11-01), Hatada
patent: 4948754 (1990-08-01), Kondo et al.
patent: 4982265 (1991-01-01), Watanabe et al.
patent: 5138438 (1992-08-01), Masayuki et al.
patent: 5162257 (1992-11-01), Yung
patent: 5289631 (1994-03-01), Koopman et al.
patent: 5293006 (1994-03-01), Yung
patent: 5342495 (1994-08-01), Tung et al.
patent: 5418186 (1995-05-01), Park et al.
patent: 5492863 (1996-02-01), Higgins, III et al.
patent: 5503286 (1996-04-01), Nye, III et al.
patent: 5508229 (1996-04-01), Baker et al.
patent: 5543032 (1996-08-01), Datta et al.
patent: 5587341 (1996-12-01), Masayuki et al.
patent: 5597469 (1997-01-01), Cary et al.
patent: 5662788 (1997-09-01), Sandhu et al.
patent: 5736456 (1998-04-01), Akram
patent: 5793117 (1998-08-01), Shimada et al.
Schiesser et al., Microdynamic Solder Pump vs Alternatives Comparative Review of Solder Bumping Techniques for Flip Chip Attach, SMI Proceedings of The Technical Program, Aug. 19-31, 1995, pp. 171-178.
Han et al., Electroplated Solder Joints for Optoelectronic Applications, 1996 Proceedings, 46th Electronic Components & Technology Conference, May 28-31, 1996, pp. 963-966.
Salonen et al., A Flip Chip Process Based on Electroplated Solder Bumps, Physica Scripta, vol. T54, Jun. 1994, pp. 230-233.
Datta et al., Electrochemical Fabrication of Mechanically Robust PbSn C4 Interconnections, J. Electrochem. Soc., vol. 142, No. 11, Nov. 1995, pp. 3779-3785.
Yu et al., Solder Bump Fabrication By Electroplating For Flip-Chip Applications, Fifteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium, Oct. 4-6, 1993, pp. 277-281.
Rinne et al., Advanced Solder Flip Chip Processes, Proceedings of The Technical Program, vol. I, Sep. 10-12, 1996, pp. 282-292.
Yung et al., Electroplated Solder Joints for Flip-Chip Applications, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 14, No. 3, Sep. 1991, pp. 549-559.
Jung et al., Reliability Investigations of Different Bumping Processes for Flip Chip and TAB Applications, Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium, Oct. 14-16, 1996, pp. 274-281.
Lin et al., Approaching a Uniform Bump Height of the Electroplated Solder Bumps on a Silicon Wafer, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B, vol. 19, No. 4, Nov. 1996, pp. 747-751.
Yung et al., Flip-Chip Process Utilizing Electroplated Solder Joints, IEPS. Proceedings of the Technical Conference, 1990 International Electronics Packaging Conference, Sep. 1990, pp. 1065-1079.
Adema et al., Flip Chip Technology: A Method for Providing Known Good Die with High Density Interconnections, SPIE Proceedings, International Conference and Exhibition, Multichip Modules, vol. 2256, Apr. 13-15, 1994, pp. 41-49.
DelMonte LA, Fabrication of Gold Bumps for Integrated Circuit Terminal Contact, 23.sup.rd Electronic Components Conference, Washington, D.C.May 14-16, 1973, PP. 21-25, XP002106381.
Database WPIL on Questel, Week 8144 London, Derwent Publications Ltd., AN 81-80514 D, Class H01B, JP 56-118210 A (HITACHI KK), abstract date not available.

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