Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2007-06-13
2010-10-05
Rodriguez, Paul L (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S014000, C716S030000
Reexamination Certificate
active
07809544
ABSTRACT:
Methods of detecting unwanted logic in a configuration bitstream for a programmable logic device (PLD). The bitstream can be reversed engineered to generate a model of the design. The model is then tested for unwanted logic, e.g., logic inserted for the purpose of monitoring or interfering with the desired functionality of the design, by applying a test suite that exercises all desired functions for the design. If some of the logic nodes in the model are not exercised by the test suite, then the unexercised nodes might constitute unwanted logic and might have been inserted for malicious purposes. To reverse engineer the bitstream, a simulation model of the unprogrammed PLD can be used. Configuration bits from the bitstream can be inserted into the model of the unprogrammed PLD. The modified model can be simplified by propagating constants through the model in response to the values inserted into the model.
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Cartier Lois D.
Chad Aniss
Maunu LeRoy D.
Rodriguez Paul L
Xilinx , Inc.
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